# US 2014/0156924 A1 · Semiconductor memory device with improved operating speed and data storage device including the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0156924 A1 - Document ID: US20140156924A1 - Status: Published application - Kind: A1 - Application number: 13/845,543 - Filed: 2013-03-18 - Published: 2014-06-05 - Earliest claimed: 2012-12-04 - Assignees: SK hynix Inc. - Applicants: SK Hynix Inc. - Inventors: Chun Woo JEON; Hwang HUH - Web page: https://patentgrep.com/patent/US20140156924A1 ## CPC - G11C 5/148: {Details of power up or power down circuits, standby circuits or recovery circuits} - G11C 5/147: {Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence)} - G11C 15/00: Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A semiconductor memory device includes a power block configured to generate an internal voltage based on an external voltage which is applied through a power pad; a circuit block configured to operate according to the internal voltage and drive memory cells; and a CAM (content addressed memory) block configured to operate according to the external voltage and store setting information necessary for driving of the memory cells. ## Claims ### Claim 1 A semiconductor memory device comprising: a power block configured to generate an internal voltage based on an external voltage; a circuit block configured to operate according to the internal voltage and drive memory cells; and a CAM (content addressed memory) block configured to operate according to the external voltage and store setting information necessary for driving of the memory cells. ### Claim 2 (depends on 1) The semiconductor memory device according to claim 1, wherein the CAM block is activated regardless of an operation mode of the semiconductor memory device. ### Claim 3 (depends on 2) The semiconductor memory device according to claim 2, wherein the CAM block is activated while the semiconductor memory device operates in an inactive mode. ### Claim 4 (depends on 3) The semiconductor memory device according to claim 3, wherein the inactive mode includes a power saving mode. ### Claim 5 (depends on 1) The semiconductor memory device according to claim 1, further comprising: a power pad configured to electrically connect to the power block and to receive the external voltage. ### Claim 6 (depends on 5) The semiconductor memory device according to claim 5, wherein the CAM block is configured to be directly provided with the external voltage through the power pad. ### Claim 7 (depends on 1) The semiconductor memory device according to claim 1, wherein the power block is configured to interrupt generation of the internal voltage while the semiconductor memory device operates in the inactive mode. ### Claim 8 (depends on 7) The semiconductor memory device according to claim 7, wherein the power block comprises: a power generating block configured to generate the internal voltage based on the external voltage; an external power blocking block configured to block the external voltage from being transferred to the power generating block while the semiconductor memory device operates in the inactive mode; and a discharging block configured to discharge the power generating block while the semiconductor memory device operates in the inactive mode. ### Claim 9 (depends on 8) The semiconductor memory device according to claim 8, wherein the discharging block is configured to provide a ground voltage to input terminals of the power generating block while the semiconductor memory device operates in the inactive mode. ### Claim 10 A data storage device comprising: a semiconductor memory device; and a controller configured to control the semiconductor memory device, wherein the semiconductor memory device comprises: a power block configured to generate an internal voltage based on an external voltage which is applied through a power pad; a circuit block configured to operate according to the internal voltage and drive memory cells; and a CAM (content addressed memory) block configured to operate according to the external voltage and store setting information necessary for driving of the memory cells. ### Claim 11 (depends on 10) The data storage device according to claim 10, wherein the semiconductor memory device is configured to operate in a power saving mode according to a power save command provided from the controller. ### Claim 12 (depends on 11) The data storage device according to claim 11, wherein the CAM block is activated while the semiconductor memory device operates in the power saving mode. ### Claim 13 (depends on 12) The data storage device according to claim 12, wherein the CAM block is configured to be directly provided with the external voltage through the power pad. ### Claim 14 (depends on 11) The data storage device according to claim 11, wherein the power block is configured to interrupt generation of the internal voltage while the semiconductor memory device operates in the power saving mode. ### Claim 15 (depends on 14) The data storage device according to claim 14, wherein the power block comprises: a power generating block configured to generate the internal voltage based on the external voltage; an external power blocking block configured to block the external voltage from being transferred to the power generating block while the semiconductor memory device operates in the power saving mode; and a discharging block configured to discharge the power generating block while the semiconductor memory device operates in the power saving mode. ### Claim 16 (depends on 11) The data storage device according to claim 11, wherein the semiconductor memory device is configured to operate in an active mode instead of the power saving mode when an activated chip select signal is provided from the controller. ### Claim 17 (depends on 10) The data storage device according to claim 10, wherein the semiconductor memory device and the controller are constituted by a solid state drive (SSD). ### Claim 18 A semiconductor system comprising: a memory device configured to operate in response to a plurality of driving modes; and a CAM (content addressed memory) block configured to is continuously operate regardless of the plurality of driving modes. ### Claim 19 (depends on 18) The system according to claim 18, wherein the plurality of driving mode includes: an active mode for providing a power to the memory device; and a deactive mode for blocking the power from the memory device. ### Claim 20 (depends on 18) The system according to claim 18, further comprising: a controller for determining the plurality of driving modes.