# US 2014/0156922 A1 · Non-volatile memory device adapted to identify itself as a boot memory > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0156922 A1 - Document ID: US20140156922A1 - Status: Published application - Kind: A1 - Application number: 14/176,320 - Filed: 2014-02-10 - Published: 2014-06-05 - Earliest claimed: 2002-12-26 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Cliff Zitlaw; Frankie F. Roohparvar; David Eggleston - Web page: https://patentgrep.com/patent/US20140156922A1 ## CPC - G06F 12/0246: {in block erasable memory, e.g. flash memory} - G06F 9/4403: {Processor initialisation} - G06F 9/4408: {Boot device selection} - G06F 12/0684: {with feedback, e.g. presence or absence of unit detected by addressing, overflow detection} - G06F 9/4401: Bootstrapping (security arrangements therefor G06F21/57) - G06F 9/4406: {Loading of operating system} - G06F 9/445: Program loading or initiating (bootstrapping G06F9/4401; security arrangements for program loading or initiating G06F21/57) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Non-volatile memory devices and methods of their operation are provided. One such non-volatile memory device has an interface and a control circuit. The non-volatile memory device is adapted to identify itself as a boot memory in response to receiving an interrogation request on the interface. ## Claims ### Claim 1 A non-volatile memory device, comprising: an interface; and a control circuit; wherein the non-volatile memory device is adapted to identify itself as a boot memory by changing a logic level of a chip select line, coupled to non-volatile memory device, in response to receiving an interrogation request on the interface. ### Claim 2 (depends on 1) The non-volatile memory device of claim 1, wherein the chip select line is a bidirectional chip select line. ### Claim 3 (depends on 1) The non-volatile memory device of claim 1, wherein receiving the interrogation request on the interface comprises a logic level of a signal, received at the non-volatile memory device over the interface, being changed from a first logic level to a second logic level. ### Claim 4 (depends on 3) The non-volatile memory device of claim 3, wherein the non-volatile memory device is adapted to keep the logic level of the chip select line changed until after the logic level of the signal received at the non-volatile memory device over the interface is returned to the first logic level. ### Claim 5 (depends on 1) The non-volatile memory device of claim 1, wherein the interrogation request is an assertion of one of a reset, an SDRAM command, a data token, and a selected combination of address, control, and data lines. ### Claim 6 (depends on 1) The non-volatile memory device of claim 1, wherein the non-volatile memory device is adapted to place one or more data values or tokens on a data bus of the synchronous interface or serially communicate one or more data values or tokens over a control line of the synchronous interface. ### Claim 7 A non-volatile memory device, comprising: an interface; and a control circuit; wherein the non-volatile memory device is adapted to receive a first signal over the interface and a second signal over a chip select line coupled to non-volatile memory device and separate from the interface; and wherein the non-volatile memory device is adapted to identify itself as a boot memory by changing a logic level of the second signal when a logic level of the first signal is being changed. ### Claim 8 (depends on 7) The non-volatile memory device of claim 7, wherein the logic level of the first signal being changed comprises the logic level of the first signal being changed from a first logic level to a second logic level, and wherein the non-volatile memory device is adapted to keep the logic level of the second signal changed while the logic level of the first signal is being returned to the first logic level. ### Claim 9 A non-volatile memory device, comprising: an interface; and a control circuit; wherein the non-volatile memory device is programmably adapted to indicate that it is the boot memory. ### Claim 10 (depends on 9) The non-volatile memory device of claim 9, wherein the non-volatile memory device identifies itself as a boot memory in response to receiving an interrogation request on the interface. ### Claim 11 A system, comprising: a memory controller; and a non-volatile memory device coupled to the memory controller; wherein the non-volatile memory device is adapted to indicate that it is a boot memory by changing a logic level of a chip select line, coupled to the memory controller and the non-volatile memory device, in response receiving an interrogation request from the memory controller over an interface that is coupled to the non-volatile memory device and the memory controller and that is separate from the chip select line. ### Claim 12 (depends on 11) The system of claim 11, wherein the non-volatile memory device is a first non-volatile memory device, and wherein a second non-volatile memory device coupled to the memory controller is configured to maintain a logic level of a chip select line, coupled to the memory controller and the second non-volatile memory device, fixed while the logic level of the chip select line, coupled to the memory controller and the first non-volatile memory device, is being changed. ### Claim 13 (depends on 11) The system of claim 11, wherein receiving an interrogation request over the interface comprises a logic level of a signal, received at the non-volatile memory device over the interface, being changed from a first logic level to a second logic level. ### Claim 14 (depends on 13) The system of claim 13, wherein the non-volatile memory device is adapted to keep the logic level of the chip select line changed until after the logic level of the signal received at the non-volatile memory device over the interface is returned to the first logic level. ### Claim 15 A system, comprising: a memory controller; and a non-volatile memory device coupled to the memory controller by an interface and a chip select line that is separate from the interface; wherein the non-volatile memory device is adapted to receive a first signal over the interface and a second signal over the chip select line; and wherein the non-volatile memory device is adapted to identify itself as a boot memory by changing a logic level of the second signal when a logic level of the first signal is being changed. ### Claim 16 (depends on 15) The system of claim 15, wherein logic level of the first signal being changed comprises the logic level of the first signal being changed from a first logic level to a second logic level, and wherein the non-volatile memory device is adapted to keep the logic level of the second signal changed while the logic level of the first signal is being returned to the first logic level. ### Claim 17 A system, comprising: a memory controller; and a non-volatile memory device coupled to the memory controller; wherein the non-volatile memory device is programmably adapted to indicate to the memory controller that it is the boot memory in response to receiving an interrogation request from the memory controller. ### Claim 18 A method of operating a non-volatile memory device, comprising: receiving an interrogation request over an interface; and indicating that the non-volatile memory device is a boot memory by changing a logic level of a chip select line, separate from the interface, in response to receiving the interrogation request. ### Claim 19 (depends on 18) The method of claim 18, wherein receiving an interrogation request over the interface comprises a logic level of a signal received at the non-volatile memory device over the interface being changed from a first logic level to a second logic level. ### Claim 20 (depends on 19) The non-volatile memory device of claim 19, further comprising: returning the logic level of the signal received at the non-volatile memory device over the interface to the first logic level; and keeping the logic level of the chip select line changed while returning the logic level of the signal received at the non-volatile memory device over the interface to the first logic level.