# US 2014/0156919 A1 · Isolation Switching For Backup Memory

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- Number: US 2014/0156919 A1
- Document ID: US20140156919A1
- Status: Published application
- Kind: A1
- Application number: 14/173,219
- Filed: 2014-02-05
- Published: 2014-06-05
- Earliest claimed: 2007-06-01
- Assignees: Netlist, Inc.
- Applicants: Netlist, Inc.
- Inventors: Chi-She Chen; Jeffrey C. Solomon; Scott H. Milton; Jayesh Bhakta
- Web page: https://patentgrep.com/patent/US20140156919A1

## CPC

- G06F 3/061: {Improving I/O performance}
- G06F 3/0634: {by changing the state or mode of one or more devices}
- G06F 3/065: {Replication mechanisms}
- G06F 3/0655: {Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices}
- G06F 3/0688: {Non-volatile semiconductor memory arrays}
- G06F 11/1072: {in multilevel memories}
- G06F 11/1441: {Resetting or repowering}
- G06F 12/00: Accessing, addressing or allocating within memory systems or architectures (digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06)
- G06F 12/0246: {in block erasable memory, e.g. flash memory}
- G11C 5/141: {Battery and back-up supplies}
- G11C 5/143: {Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels (G11C5/148 takes precedence); Switching between alternative supplies (G11C5/141 takes precedence)}
- G11C 7/1072: {for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories}
- G11C 11/005: {comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells}
- G11C 14/0018: {whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor}
- G11C 29/52: Protection of memory contents; Detection of errors in memory contents
- G06F 11/2015: {Redundant power supplies (power supply failure G06F1/30)}
- G06F 2212/7201: Logical to physical mapping or translation of blocks or pages
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Certain embodiments described herein include a memory system having a volatile memory subsystem, a non-volatile memory subsystem, a controller coupled to the non-volatile memory subsystem, and a circuit coupled to the volatile memory subsystem, to the controller, and to a host system. In a first mode of operation, the circuit is operable to selectively isolate the controller from the volatile memory subsystem, and to selectively couple the volatile memory subsystem to the host system to allow data to be communicated between the volatile memory subsystem and the host system. In a second mode of operation, the circuit is operable to selectively couple the controller to the volatile memory subsystem to allow data to be communicated between the volatile memory subsystem and the nonvolatile memory subsystem using the controller, and the circuit is operable to selectively isolate the volatile memory subsystem from the host system.

## Claims

### Claim 1

A memory system comprising:
a volatile memory subsystem;
a non-volatile memory subsystem;
a controller coupled to the non-volatile memory subsystem; and
a circuit coupled to the volatile memory subsystem, to the controller, and to a host system, wherein:
in a first mode of operation, the circuit is operable to selectively isolate the controller from the volatile memory subsystem, and to selectively couple the volatile memory subsystem to the host system to allow data to be communicated between the volatile memory subsystem and the host system, and
in a second mode of operation, the circuit is operable to selectively couple the controller to the volatile memory subsystem to allow data to be communicated between the volatile memory subsystem and the nonvolatile memory subsystem using the controller, and the circuit is operable to selectively isolate the volatile memory subsystem from the host system.