# US 2014/0156918 A1 · Storage devices including memory device and methods of operating the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0156918 A1 - Document ID: US20140156918A1 - Status: Published application - Kind: A1 - Application number: 14/096,491 - Filed: 2013-12-04 - Published: 2014-06-05 - Earliest claimed: 2012-12-04 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Hong-Suk CHOI; Su-Ryun LEE; Chun-Um KONG; Youn-Won PARK - Web page: https://patentgrep.com/patent/US20140156918A1 ## CPC - G06F 12/0246: {in block erasable memory, e.g. flash memory} - G11C 11/5628: {Programming or writing circuits; Data input circuits} - G11C 2211/5646: Multilevel memory with flag bits, e.g. for showing that a "first page" of a word line is programmed but not a "second page" - G11C 2211/5648: Multilevel memory programming, reading or erasing operations wherein the order or sequence of the operations is relevant - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Storage devices including a memory device and methods of operating the storage devices are provided. The storage devices may include a controller which is configured to program first bit data and second bit data paired with the first bit data into a memory device. The first bit data may be less significant bit data than the second bit data. The controller may be configured to selectively perform or skip backup of the first bit data when programming the second bit data. ## Claims ### Claim 1 A storage device, comprising: a flash memory; and a controller configured to program first bit data and second bit data into the flash memory, wherein when programming the second bit data the controller is configured to omit a backup operation for the first bit data if a task of programming the first bit data is being executed and is configured to perform the backup operation for the first bit data if the task of programming the first bit data is not being executed, and wherein the first bit data is less significant bit data than the second bit data. ### Claim 2 (depends on 1) The storage device of claim 1, wherein the controller is configured to determine that the task of programming the first bit data is being executed if a transaction ID of the first bit data is identical to a transaction ID of the second bit data. ### Claim 3 (depends on 2) The storage device of claim 2, wherein the controller is configured to allocate the transaction IDs of the first bit data and the second bit data to a same transaction, and the transaction comprises one or more tasks of programming one or more pieces of data into the flash memory. ### Claim 4 (depends on 3) The storage device of claim 3, wherein the tasks included in the transaction are prioritized and can be processed simultaneously. ### Claim 5 (depends on 1) The storage device of claim 1, wherein the controller is configured to determine that the task of programming the first bit data is being executed if a last confirm flag has not been set for the task of programming the first bit data. ### Claim 6 (depends on 5) The storage device of claim 5, wherein the controller is configured to set the last confirm flag when the task of programming the first bit data is completed. ### Claim 7 (depends on 5) The storage device of claim 5, wherein the controller is configured to determine that the task of programming the first bit data is not being executed if a sequence number of the first bit data is not greater than a start sequence number of the task of programming the first bit data. ### Claim 8 (depends on 7) The storage device of claim 7, wherein the controller is configured to update the start sequence number and store the updated start sequence number when the task of programming the first bit data is completed. ### Claim 9 A storage device, comprising: a flash memory; and a controller configured to program first bit data and second bit data into the flash memory, wherein the controller is configured to omit backing up the first bit data when programming the first bit data and the second bit data in a same transaction and is configured to perform backing up the first bit data when programming the first bit data and the second bit data in different transactions, and wherein the first bit data is less significant bit data than the second bit data, each of the transactions comprises one or more prioritized tasks, and the tasks included in each of the transactions can be processed simultaneously. ### Claim 10 (depends on 9) The storage device of claim 9, wherein if a transaction ID of the first bit data is identical to a transaction ID of the second bit data, the controller is configured to determine that the first bit data and the second bit data are programmed in the same transaction. ### Claim 11 (depends on 10) The storage device of claim 10, wherein a unique transaction ID is allocated to the transaction, and the controller is configured to store the transaction ID of the first bit data. ### Claim 12 (depends on 9) The storage device of claim 9, wherein if the transaction ID of the first bit data is different from the transaction ID of the second bit data, the controller is configured to determine that the first bit data and the second bit data are programmed in different transactions. ### Claim 13 (depends on 12) The storage device of claim 12, wherein a unique transaction ID is allocated to each of the different transactions, and the controller is configured to store the transaction ID of the first bit data. ### Claim 14 (depends on 9) The storage device of claim 9, wherein when each of the transactions which comprises the tasks is completed, the controller is configured to transmit a complete signal to a host. ### Claim 15 (depends on 9) The storage device of claim 9, wherein a size of each of the transactions is determined by at least one of a channel, way, and super block of the flash memory. ### Claim 16 A storage device, comprising: a flash memory comprising a memory cell configured to store a least significant bit (LSB) data and a most significant bit (MSB) data; and a controller configured to selectively skip backup of the LSB data when programming the MSB data based on an operational parameter associated with the LSB data. ### Claim 17 (depends on 16) The storage device of claim 16, wherein: the operational parameter comprises a transaction ID of the LSB; and the controller is configured to perform the backup of the LSB data when programming the MSB data if the transaction ID of the LSB data and a transaction ID of the MSB data are different, and is configured to skip the backup of the LSB data when programming the MSB data if the transaction ID of the LSB data and the transaction ID of the MSB data are equal. ### Claim 18 (depends on 17) The storage device of claim 17, wherein the controller is configured to allocate the transaction IDs to transactions which comprise programming tasks of the LSB data and the MSB data. ### Claim 19 (depends on 16) The storage device of claim 16, wherein: the operational parameter comprises a last confirm flag configured to indicate whether a programming task of the LSB data is completed; and the controller is configured to perform the backup of the LSB data when programming the MSB data if the last confirm flag indicates that the programming task of the LSB data is completed. ### Claim 20 (depends on 19) The storage device of claim 19, wherein: the operational parameter further comprises a sequence number of the LSB data; and the controller is configured to perform the backup of the LSB data when programming the MSB data if the sequence number of the LSB data is smaller than a start sequence number, and is configured to skip the backup of the LSB data when programming the MSB data if the sequence number of the LSB data is equal to or larger than the start sequence number.