# US 2014/0156917 A1 · Storage Devices, Flash Memories, and Methods of Operating Storage Devices > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0156917 A1 - Document ID: US20140156917A1 - Status: Published application - Kind: A1 - Application number: 14/095,240 - Filed: 2013-12-03 - Published: 2014-06-05 - Earliest claimed: 2012-12-04 - Assignees: Samsung Electronics Co., Ltd. - Inventors: Hong-Suk Choi; Kyu-Hyung Kim; Do-Sam Kim; Hyun-Sik Yun - Web page: https://patentgrep.com/patent/US20140156917A1 ## CPC - H10W 20/493: {Fuses, i.e. interconnections changeable from conductive to non-conductive} - G06F 12/0246: {in block erasable memory, e.g. flash memory} - H10B 20/25: One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links - H10W 20/48: Insulating materials thereof - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H10B: ELECTRONIC MEMORY DEVICES ## Abstract A storage device is provided including a flash memory, and a controller programming first bit data and second bit data into the flash memory and not backing up the first bit data when programming the first bit data and the second bit data in the same transaction and backing up the first bit data when programming the first bit data and the second bit data in different transactions, wherein the first bit data is less significant bit data than the second bit data, and each of the transactions is determined using a sync signal transmitted from a host. ## Claims ### Claim 1 A storage device comprising: a flash memory; and a controller programming first bit data and second bit data into the flash memory, wherein the controller does not back up the first bit data when programming the first bit data and the second bit data in a same transaction and backs up the first bit data when programming the first bit data and the second bit data in different transactions; wherein the first bit data is less significant bit data than the second bit data; and wherein each of the transactions is determined using a sync signal transmitted from a host. ### Claim 2 (depends on 1) The storage device of claim 1, wherein if a sequence number of the first bit data is greater than a reference sequence number, the controller is configured to determine that the first bit data and the second bit data are programmed in a same transaction. ### Claim 3 (depends on 2) The storage device of claim 2, wherein the reference sequence number is a sequence number of bit data programmed last in a previous transaction. ### Claim 4 (depends on 3) The storage device of claim 3, wherein when a transaction is terminated, the controller is configured to update the reference sequence number and store the updated reference sequence number. ### Claim 5 (depends on 1) The storage device of claim 1, wherein the controller is configured to program a plurality of bit data into the flash memory according to the sync signal. ### Claim 6 (depends on 5) The storage device of claim 5, wherein each of the transactions comprises one or more tasks, and the tasks comprise programming the plurality of bit data into the flash memory using the controller. ### Claim 7 (depends on 1) The storage device of claim 1, wherein the controller is configured to back up the first bit data into a backup block of the flash memory. ### Claim 8 (depends on 7) The storage device of claim 7, wherein the controller is configured to program the first bit data and the second bit data into a user block of the flash memory. ### Claim 9 A storage device comprising: a flash memory; and a controller configured to program first bit data and second bit data into the flash memory, wherein when programming the second bit data in a current transaction the controller does not back up the first bit data in the current transaction if a sequence number of the first bit data is greater than a reference sequence number and backs up the first bit data in the current transaction if the sequence number of the first bit data is not greater than the reference sequence number; wherein the first bit data is less significant bit data than the second bit data; and wherein the reference sequence number is a sequence number of bit data programmed last in a previous transaction. ### Claim 10 (depends on 9) The storage device of claim 9, wherein each of the transactions is determined using a sync signal transmitted from a host. ### Claim 11 (depends on 10) The storage device of claim 10, wherein when a transaction is terminated, the controller is configured to update the reference sequence number and store the updated reference sequence number. ### Claim 12 (depends on 9) The storage device of claim 9, wherein if the sequence number of the first data is greater than the reference sequence number, the controller is configured to program the first bit data and the second bit data in a same transaction. ### Claim 13 (depends on 9) The storage device of claim 9, wherein the controller is configured to back up the first bit data into a backup block of the flash memory. ### Claim 14 (depends on 13) The storage device of claim 13, wherein the controller is configured to program the first bit data and the second bit data into a user block of the flash memory. ### Claim 15 A flash memory comprising: a first block, first bit data and second bit data being programmed in the first block; and a second block, wherein the first bit data is not backed up in the second block when the first bit data and the second bit data are programmed in a same transaction and the first bit data is backed up in the second block when the first bit data and the second bit data are programmed in different transactions; wherein the first bit data is less significant bit data than the second bit data; and wherein each of the transactions is determined using a sync signal transmitted from a host. ### Claim 16 (depends on 15) The flash memory of claim 15, further comprising a controller that does not back up the first bit data into the second block if a sequence number of the first data is greater than a reference sequence number. ### Claim 17 (depends on 16) The flash memory of claim 16, wherein the reference sequence number is a sequence number of bit data programmed last in a previous transaction. ### Claim 18 (depends on 17) The flash memory of claim 17, wherein when a transaction is terminated, the controller is configured to update the reference sequence number and store the updated reference sequence number. ### Claim 19 (depends on 15) The flash memory of claim 15, wherein a plurality of bit data are programmed into the first block according to the sync signal. ### Claim 20 (depends on 19) The flash memory of claim 19, wherein each of the transactions comprises one or more tasks, and the tasks comprise programming the plurality of bit data into the first block using the controller. ### Claim 21 A method of operating a storage device, the method comprising: programming first bit data into a flash memory; determining whether a sequence number of the first bit data is greater than a reference sequence number before programming second bit data into the flash memory; and not backing up the first bit data if the sequence number of the first bit data is greater than the reference sequence number, wherein the first bit data is less significant bit data than the second bit data, and the reference sequence number is a sequence number of bit data programmed last in a previous transaction. ### Claim 22 (depends on 21) The method of claim 21, further comprising backing up the first bit data if the sequence number of the first bit data is not greater than the reference sequence number. ### Claim 23 (depends on 22) The method of claim 22, wherein in the programming of the first bit data into the flash memory, the first bit data is programmed into a user block of the flash memory, and in the backing up of the first bit data, the first bit data is backed up into a backup block of the flash memory. ### Claim 24 (depends on 21) The method of claim 21, wherein each of the transactions is determined using a sync signal transmitted from a host. ### Claim 25 (depends on 24) The method of claim 24, further comprising: determining whether a current transaction is terminated; and updating the reference sequence number to a sequence number of bit data programmed last in the current transaction and storing the updated reference sequence number when the current transaction is terminated.