# US 2014/0156915 A1 · Partitioning a flash memory data storage device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0156915 A1 - Document ID: US20140156915A1 - Status: Published application - Kind: A1 - Application number: 14/089,397 - Filed: 2013-11-25 - Published: 2014-06-05 - Earliest claimed: 2009-04-08 - Assignees: Google Inc. - Applicants: Google Inc. - Inventors: Albert T. Borchers; Andrew T. Swing; Robert S. Sprinkle - Web page: https://patentgrep.com/patent/US20140156915A1 ## CPC - G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]} - G06F 3/0613: {in relation to throughput} - G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors} - G06F 3/0644: {Management of space entities, e.g. partitions, extents, pools} - G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling} - G06F 12/0246: {in block erasable memory, e.g. flash memory} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A method of partitioning a data storage device that has a plurality of memory chips includes determining a number memory chips in the data storage device, defining, via a host coupled to the data storage device, a first partition of the data storage device, where the first partition includes a first subset of the plurality of memory chips, defining a second partition of the data storage device via the host where the second partition includes a second subset of the plurality of memory chips, such that the first subset does not include any memory chips of the second subset and wherein the second subset does not include any memory chips of the first subset. ## Claims ### Claim 1 (canceled) ### Claim 2 A method of partitioning a data storage device, the method comprising: receiving, via an interface operably coupling a host with the data storage device, information indicating a number of a plurality of flash memory chips in the data storage device, a first portion of the plurality of flash memory chips being implemented in a first memory channel and a second portion of the plurality of flash memory chips being implemented in a second memory channel; defining, by the host, a first partition of the data storage device, the first partition including a first subset of the plurality of flash memory chips that includes one or more memory chips of the first memory channel and one or more memory chips of the second memory channel; and defining, by the host, a second partition of the data storage device, the second partition including a second subset of the plurality of flash memory chips that does not include any flash memory chips of the first subset, a boundary between the first partition and the second partition being defined by the first subset of memory chips and the second subset of memory chip. ### Claim 3 (depends on 2) The method of claim 2, wherein the interface is a PCIe interface. ### Claim 4 (depends on 2) The method of claim 2, further comprising: transmitting first data, via the interface, from the host to the data storage device; and writing the first data to the first partition while reading second data from the second partition. ### Claim 5 (depends on 2) The method of claim 2, further comprising defining, by the host, an address location in the data storage device to which to write data from the host, wherein the address location specifies that the data be written to a specific one of the plurality of memory chips. ### Claim 6 (depends on 2) The method of claim 2, wherein the data storage device includes a plurality of physical channels for communication of data between the host and the plurality of memory chips, each channel being operably connected to a different plurality of the memory chips, the method further comprising: determining a number of the plurality of physical channels; determining a first subset of the channels, wherein channels of the first subset of the channels are operably connected only to memory chips of the first subset of memory chips; determining a second subset of the channels, wherein channels of the second subset of the channels are operably connected only to memory chips of the second subset of memory chips; and defining, in the host, an address location in the data storage device to which to write data from the host, wherein the address location specifies that the data be written to a specific one of the plurality of memory chips through a specific channel. ### Claim 7 (depends on 6) The method of claim 6, wherein the second partition includes memory chips that are operably connected to a single channel. ### Claim 8 (depends on 2) The method of claim 2, further comprising: re-defining, via the host coupled to the data storage device, the first partition of the data storage device to include a third subset of the plurality of memory chips, wherein the third subset is different from the first subset, and wherein the third subset does not include any memory chips of the second subset. ### Claim 9 (depends on 8) The method of claim 8, further comprising: receiving an indication that one of the memory chips in the first subset has failed or is approaching failure, wherein re-defining the first partition includes defining the third subset as the first subset of memory chips but for the memory chip that has failed or that is approaching failure. ### Claim 10 An apparatus comprising: a data storage device including a plurality of memory chips, a first portion of the plurality of memory chips being implemented in a first memory channel and a second portion of the plurality of memory chips being implemented in a second memory channel; an interface operably coupled with the data storage device; and a host operably coupled with the data storage device via the interface, the host including: a configuration detection engine configured to communicate with the data storage device, via the interface, to detect a number of the plurality of memory chips in the data storage device; and a partition engine configured to define a first partition of the data storage device, the first partition including a first subset of the plurality of memory chips and to define a second partition of the data storage device, the second partition including a second subset of the plurality of memory chips, the first subset including one or more memory chips of the first memory channel and one or more memory chips of the second memory channel; the first subset not including any memory chips of the second subset; and a boundary between the first partition and second partition being defined by the first subset of memory chips and the second subset of memory chips. ### Claim 11 (depends on 10) The apparatus of claim 10, wherein: the host is configured to transmit, via the interface, an information request command to the data storage device; and the data storage device is configured to transmit, via the interface upon receiving the information request command, information indicating the number of the plurality of memory chips in the data storage device. ### Claim 12 (depends on 10) The apparatus of claim 10, wherein the host further comprises an address assignment engine configured to assign a memory address to data to be written to the data storage device, wherein the assigned memory address specifies that the data be written to a specific one of the plurality of memory chips. ### Claim 13 (depends on 10) The apparatus of claim 10, wherein: the data storage device includes a plurality of channels for communication of data between the host and the plurality of memory chips, each channel being operably connected to a different plurality of the memory chips, the configuration detection engine is further configured to detect a number of the plurality of channels in the data storage device, the partition engine is further configured to define a first subset of the channels, channels of the first subset of the channels being operably connected only to memory chips of the first subset of memory chips, and the partition engine is further configured to define a second subset of the channels, channels of the second subset of the channels being operably connected only to memory chips of the second subset of memory chips. ### Claim 14 (depends on 13) The apparatus of claim 13, wherein the host further comprises an address assignment engine configured to assign a memory address to data to be written to the data storage device, the assigned memory address specifying that the data be written to a specific one of the plurality of memory chips through a specific channel. ### Claim 15 (depends on 13) The apparatus of claim 13, wherein the second partition includes memory chips that are operably connected to a single channel. ### Claim 16 (depends on 10) The apparatus of claim 10, wherein: the partition engine is further configured to re-define the first partition of the data storage device to include a third subset of the plurality of memory chips, the third subset is different from the first subset, and the third subset does not include any memory chips of the second subset. ### Claim 17 (depends on 16) The apparatus of claim 16, wherein: the partition engine is further configured to receive an indication, via the interface, that one of the memory chips in the first subset has failed or is approaching failure, and re-defining the first partition to include the third subset of the plurality of memory chips includes defining the third subset as the first subset of memory chips but for the memory chip that has failed or that is approaching failure. ### Claim 18 (depends on 10) The apparatus of claim 10, wherein the interface is a PCIe interface. ### Claim 19 A method of partitioning a data storage device, wherein the device includes a plurality of memory chips, the method comprising: reading, by a host via a PCIe interface operably coupling the host with the data storage device, a physical configuration of the data storage device, the physical configuration including a number of the plurality of memory chips in the data storage device, a first portion of the plurality of memory chips being implemented in a first memory channel and a second portion of the plurality of memory chips being implemented in a second memory channel; reading, but the host via the PCIe interface, a partitioning scheme for the data storage device; defining, via by the host, a first partition of the data storage device, the first partition including a first subset of the plurality of memory chips; allocating, by the host, a logical to physical memory map for the first partition; defining, by the host, a second partition of the data storage device, the second partition including a second subset of the plurality of memory chips; and allocating, by the host, a logical to physical memory map for the second partition, the first subset including one or more memory chips of the first memory channel and one or more memory chips of the second memory channel; the first subset not including any memory chips of the second subset; and a boundary between the first partition and second partition is defined by the first subset of memory chips and the second subset of memory chips. ### Claim 20 (depends on 19) The method of claim 19, further comprising: transmitting, via the PCIe interface, first data from the host to the data storage device; and by the data storage device, writing the first data to the first partition while reading second data from the second partition. ### Claim 21 (depends on 19) The method of claim 19, wherein the data storage device includes a plurality of physical channels for communication of data between the host and the plurality of memory chips, each channel being operably connected to a different plurality of the memory chips, wherein the physical configuration of the data storage device further includes the number of the plurality of memory chips in the data storage device, the method further comprising: determining a first subset of the channels, wherein channels of the first subset of the channels are operably connected only to memory chips of the first subset of memory chips; determining a second subset of the channels, wherein channels of the second subset of the channels are operably connected only to memory chips of the second subset of memory chips; and defining, by the host, an address location in the data storage device to which to write data from the host, wherein the address location specifies that the data be written to a specific one of the plurality of memory chips through a specific channel.