# US 2014/0156905 A1 · System and Method for Intelligent Platform Management Interface Keyboard Controller Style Interface Multiplexing

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- Number: US 2014/0156905 A1
- Document ID: US20140156905A1
- Status: Published application
- Kind: A1
- Application number: 13/691,483
- Filed: 2012-11-30
- Published: 2014-06-05
- Earliest claimed: 2012-11-30
- Assignees: Dell Products L.P.
- Inventors: Wade A. Butcher; Richard L. Holmberg
- Web page: https://patentgrep.com/patent/US20140156905A1

## CPC

- G06F 13/36: for access to common bus or bus system
- G06F 13/24: using interrupt (G06F13/32 takes precedence)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

An information handling system includes a processing node, an input/output (I/O) module coupled to the processing node via a high bandwidth interface, and a service processor coupled to the I/O module via a multi-master interface. A transaction between the processing node and the service processor that is targeted to a low pin count (LPC) bus is executed between the processing node and the service processor via the high bandwidth interface and the multi-master interface.

## Claims

### Claim 1

An information handling system comprising:
a first processing node;
a first input/output (I/O) module coupled to the first processing node via a first high bandwidth interface; and
a service processor coupled to the first I/O module via a multi-master interface;
wherein a first transaction between the first processing node and the service processor that is targeted to a low pin count (LPC) bus is executed between the first processing node and the service processor via the first high bandwidth interface and the multi-master interface.

### Claim 2 (depends on 1)

The information handling system of claim 1, wherein the first transaction is intercepted by a first I/O trap of the first I/O module, such that the first transaction is not executed on the LPC bus.

### Claim 3 (depends on 2)

The information handling system of claim 2, wherein the first I/O module is operable to generate a first system management interrupt in response to the first transaction being intercepted by the first I/O trap.

### Claim 4 (depends on 3)

The information handling system of claim 3, wherein:
the first system management interrupt is received by a first system management interrupt handler of the first processing node; and
the first system management interrupt handler redirects the first transaction from the LPC bus to the first high bandwidth interface.

### Claim 5 (depends on 1)

The information handling system of claim 1, further comprising:
a second processing node; and
a second input/output (I/O) module coupled to the first processing node via a second high bandwidth interface;
wherein:
the service processor is coupled to the second I/O module via the multi-master interface; and
a second transaction between the second processing node and the service processor that is targeted to the low pin count (LPC) bus is executed between the second processing node and the service processor via the second high bandwidth interface and the multi-master interface.

### Claim 6 (depends on 5)

The information handling system of claim 5, wherein:
the second transaction is intercepted by a second I/O trap of the second I/O module, such that the second transaction is not executed on the LPC bus;
the second I/O module is operable to generate a second system management interrupt in response to the second transaction being intercepted by the second I/O trap; and
the second system management interrupt is received by a second system management interrupt handler of the second processing node; and
the second system management interrupt handler redirects the second transaction from the LPC bus to the second high bandwidth interface.

### Claim 7 (depends on 1)

The information handling system of claim 1, wherein the first transaction is generated by a first keyboard control style handler associated with the first processing node.

### Claim 8 (depends on 7)

The information handling system of claim 7, wherein the first transaction is received by a second keyboard control style handler associated with the service processor.

### Claim 9 (depends on 1)

The information handling system of claim 1, further comprising:
a system-on-a-chip device that includes the processing node, the I/O module, and the first high bandwidth interface.

### Claim 10

A method comprising:
receiving, at a first processing node, a first transaction between the first processing node and a service processor that is targeted to a low pin count (LPC) bus;
sending the first transaction to the service processor via a first high bandwidth interface between the first processing node and a first input/output (I/O) module, and via a multi-master interface between the first I/O module and the service processor.

### Claim 11 (depends on 10)

The method of claim 10, further comprising:
receiving the first transaction at the first I/O module; and
intercepting the first transaction by a first I/O trap of the first I/O module, such that the first transaction is not executed on the LPC bus.

### Claim 12 (depends on 11)

The method of claim 11, further comprising:
generating a first system management interrupt in response to the first transaction being intercepted by the first I/O trap.

### Claim 13 (depends on 12)

The method of claim 12, further comprising:
receiving, by a first system management interrupt handler of the first processing node, the first system management interrupt; and
redirecting, by the first system management interrupt handler, the first transaction from the LPC bus to the first high bandwidth interface.

### Claim 14 (depends on 10)

The method of claim 10, further comprising:
receiving, at a second processing node, a second transaction between the second processing node and the service processor that is targeted to the LPC bus; and
sending the first transaction to the service processor via a second high bandwidth interface between the second processing node and a second I/O module, and via the multi-master interface to the service processor.

### Claim 15 (depends on 14)

The method of claim 14, further comprising:
receiving the second transaction at the second I/O module;
intercepting the second transaction by a second I/O trap of the second I/O module, such that the second transaction is not executed on the LPC bus;
generating a second system management interrupt in response to the second transaction being intercepted by the second I/O trap;
receiving, by a second system management interrupt handler of the second processing node, the second system management interrupt; and
redirecting, by the second system management interrupt handler, the second transaction from the LPC bus to the second high bandwidth interface.

### Claim 16 (depends on 10)

The method of claim 10, wherein the first transaction is generated by a first keyboard control style handler associated with the first processing node.

### Claim 17 (depends on 16)

The method of claim 16, wherein the first transaction is received by a second keyboard control style handler associated with the service processor.

### Claim 18

A non-transitory computer-readable medium including code for carrying out a method, the method comprising:
receiving, at a first processing node, a first transaction between the first processing node and a service processor that is targeted to a low pin count (LPC) bus;
sending the first transaction to the service processor via a first high bandwidth interface between the first processing node and a first input/output (I/O) module, and via a multi-master interface between the first I/O module and the service processor.

### Claim 19 (depends on 18)

The computer-readable medium of claim 18, the method further comprising:
receiving the first transaction at the first I/O module;
intercepting the first transaction by a first I/O trap of the first I/O module, such that the first transaction is not executed on the LPC bus; and
generating a first system management interrupt in response to the first transaction being intercepted by the first I/O trap.

### Claim 20 (depends on 19)

The computer-readable medium of claim 19, the method further comprising:
receiving, by a first system management interrupt handler of the first processing node, the first system management interrupt; and
redirecting, by the first system management interrupt handler, the first transaction from the LPC bus to the first high bandwidth interface.