# US 2014/0156904 A1 · Bus controller > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0156904 A1 - Document ID: US20140156904A1 - Status: Published application - Kind: A1 - Application number: 14/170,728 - Filed: 2014-02-03 - Published: 2014-06-05 - Earliest claimed: 2003-07-17 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Luca De Santis; Pasquale Conenna - Web page: https://patentgrep.com/patent/US20140156904A1 ## CPC - G06F 12/0246: {in block erasable memory, e.g. flash memory} - G06F 12/0875: with dedicated cache, e.g. instruction or stack - G06F 13/16: for access to memory bus (G06F13/28 takes precedence) - G06F 13/1694: {Configuration of memory controller to different memory types} - G06F 2212/202: Non-volatile memory - G06F 2212/452: Instruction code - G11C 16/10: Programming or data input circuits - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A bus controller has a displacer, an arithmetic logic unit coupled to the displacer, and a replacer selectively coupled to the displacer and the arithmetic logic unit. ## Claims ### Claim 1 A bus controller, comprising: a displacer; an arithmetic logic unit coupled to the displacer; and a replacer selectively coupled to the displacer and the arithmetic logic unit. ### Claim 2 (depends on 1) The bus controller of claim 1, wherein the displacer is configured to receive data and to pass that data without performing any operations on the data or to displace data contained in one portion of a received data field to another portion of the received data field. ### Claim 3 (depends on 1) The bus controller of claim 1, wherein the arithmetic logic unit is configured to perform operations selected from the group consisting of changing data, performing logical operations on data, and masking data. ### Claim 4 (depends on 1) The bus controller of claim 1, wherein the arithmetic logic unit data is configured to receive data from the displacer and/or data from a code storage device and to perform operations on the data from the displacer or the data from the code storage device or to perform operations on a combination of the data from the displacer and the data from the code storage device. ### Claim 5 (depends on 4) The bus controller of claim 4, wherein the arithmetic logic unit is further configured to mask and/or change a result of the operations performed on the combination of the data from the displacer and the data from the code storage device. ### Claim 6 (depends on 4) The bus controller of claim 4, wherein the operations on the combination of the data from the displacer and the data from the code storage device comprise ANDing or ORing operations. ### Claim 7 (depends on 6) The bus controller of claim 6, wherein the arithmetic logic unit is configured to mask and/or decrement the result of the ANDing or ORing operations. ### Claim 8 (depends on 1) The bus controller of claim 1, wherein the replacer is configured to selectively receive data from the displacer, the arithmetic logic unit, data that is also received at the displacer, and/or data contained in an instruction from a code storage device. ### Claim 9 (depends on 8) The bus controller of claim 8, wherein the replacer is configured to create data from combinations of the data received thereat or to pass the data received thereat without performing any operations on that data. ### Claim 10 (depends on 1) The bus controller of claim 1, wherein the displacer, the arithmetic logic unit, and the replacer are configured to perform operations on data received thereat in response to instructions from a code storage device of a memory device. ### Claim 11 (depends on 1) The bus controller of claim 1, wherein the displacer is configured to displace data from a most significant byte to a least significant byte of a word received at the displacer. ### Claim 12 A bus controller, comprising: a displacer; an arithmetic logic unit coupled to an output of the displacer; a first multiplexer coupled to a plurality of outputs of the arithmetic logic unit; second and third multiplexers coupled to an output of the first multiplexer; and a replacer coupled to an output of the second multiplexer and an output of the third multiplexer, wherein the replacer is selectively coupled to the displacer and the arithmetic logic unit through the first, second, and third multiplexers. ### Claim 13 (depends on 12) The bus controller of claim 12, wherein the plurality of outputs of the arithmetic logic unit output data are the result of different processing operations performed by the arithmetic logic unit. ### Claim 14 (depends on 12) The bus controller of claim 12, further comprising a fourth multiplexer coupled to an input of the third multiplexer and configured to receive inputs from externally of the bus controller. ### Claim 15 (depends on 12) The bus controller of claim 12, further comprising a fourth multiplexer coupled to the replacer and configured to receive inputs from externally of the bus controller. ### Claim 16 (depends on 15) The bus controller of claim 15, wherein the replacer is configured to create data by combining data inputs from at least one of the second and third multiplexers and the fourth multiplexer. ### Claim 17 A bus controller, comprising: a displacer; an arithmetic logic unit coupled to the displacer and configured to receive an output from the displacer and configured to receive an input from externally of the bus controller; a first multiplexer coupled to the arithmetic logic unit and configured to select between outputs of the arithmetic logic unit that are the result of different processing operations performed by arithmetic logic unit; second and third multiplexers each configured to receive an output from the first multiplexer; a replacer configured to receive an output from the second multiplexer and an output from the third multiplexer, wherein the replacer is selectively coupled to the displacer and the arithmetic logic unit through the first, second, and third multiplexers; a fourth multiplexer configured to select between two inputs to the fourth multiplexer from externally of the bus controller for output from the fourth multiplexer, wherein the second multiplexer is further configured to receive the output from the fourth multiplexer; and a fifth multiplexer configured to select between two inputs to the fifth multiplexer from externally of the bus controller for output to the replacer. ### Claim 18 (depends on 17) The bus controller of claim 17, wherein the displacer is configured to receive one of the inputs to the fifth multiplexer. ### Claim 19 (depends on 17) The bus controller of claim 17, wherein the second multiplexer and the third multiplexer are configured to receive a same input from externally of the bus controller. ### Claim 20 (depends on 17) The bus controller of claim 17, wherein the arithmetic logic unit and the third multiplexer are configured to receive a same input from externally of the bus controller.