# US 2014/0156902 A1 · Line coding for low-radio noise memory interfaces

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- Number: US 2014/0156902 A1
- Document ID: US20140156902A1
- Status: Published application
- Kind: A1
- Application number: 13/995,804
- Filed: 2012-03-30
- Published: 2014-06-05
- Earliest claimed: 2012-03-30
- Assignees: Intel Corporation
- Inventors: William Dawson Kesling; Howard S. David; Michael Williams
- Web page: https://patentgrep.com/patent/US20140156902A1

## CPC

- G06F 13/28: using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence)
- G06F 13/4243: {with synchronous protocol}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

According to some embodiments, a method and apparatus are provided to receive a first data burst associated with a first data line and a second data burst associated with a second data line, determine a first one or more stuff bits to be transmitted after the first data burst and a second one or more stuff bits to be transmitted after the second data burst, and output data comprising the first data burst and the first one or more stuff bits and the second data burst and the second one or more stuff bits.

## Claims

### Claim 1

A method comprising:
receiving a first data burst associated with a first data line;
receiving a second data burst associated with a second data line;
determining a first one or more stuff bits to be transmitted after the first data burst and a second one or more stuff bits to be transmitted after the second data burst; and
outputting data comprising the first data burst, the first one or more stuff bits, the second data burst and the second one or more stuff bits.

### Claim 2 (depends on 1)

The method of claim 1, wherein the determining is based on an amount of interference reduction produced by a combination of the first one or more stuff bits and the second one or more stuff bits.

### Claim 3 (depends on 2)

The method of claim 2, wherein the determining the first one or more stuff bits and the second one or more stuff bits comprises:
determining an amount of interference reduction associated with each possible combination of the first one or more stuff bits and the second one or more stuff bits; and
determining a combination that produces more interference reduction than remaining combinations of the first one or more stuff bits and the second one or more stuff bits.

### Claim 4 (depends on 3)

The method of claim 3, wherein determining the first one or more stuff bits and the second one or more stuff bits is further based on an amount of residual interference from a previous data burst.

### Claim 5 (depends on 1)

The method of claim 1, further comprising:
receiving a third data burst associated with the first data line and a fourth data burst associated with the second data line.

### Claim 6 (depends on 5)

The method of claim 5, further comprising:
creating a first time bubble between the first data burst and the third data burst; and
creating a second time bubble between the second data burst and the fourth data burst.

### Claim 7 (depends on 6)

The method of claim 6, wherein the first time bubble and the second time bubble are associated with a register of a memory controller.

### Claim 8

An apparatus comprising:
a memory bus comprising a plurality of data lines;
a memory controller, the memory controller to:
receive a first data burst associated with a first data line;
receive a second data burst associated with a second data line;
determine a first one or more stuff bits to be transmitted after the first data burst and a second one or more stuff bits to be transmitted after the second data burst based on an amount of interference reduction produced by a combination of the first one or more stuff bits and the second one or more stuff bits; and
output data comprising the first data burst, the first one or more stuff bits, the second data burst and the second one or more stuff bits

### Claim 9 (depends on 8)

The apparatus of claim 8, wherein determining the first one or more stuff bits and the second one or more stuff bits comprises:
determining an amount of interference reduction associated with each possible combination of the first one or more stuff bits and the second one or more stuff bits; and
determining a combination that produces more interference reduction with the wireless interface than remaining combinations of the first one or more stuff bits and the second one or more stuff bits.

### Claim 10 (depends on 9)

The apparatus of claim 9, wherein determining the first one or more stuff bits and the second one or more stuff bits is further based on an amount of residual interference from a previous data burst.

### Claim 11 (depends on 8)

The apparatus of claim 8, wherein the memory controller is to further:
receive a third data burst associated with the first data line and a fourth data burst associated with the second data line.

### Claim 12 (depends on 11)

The apparatus of claim 11, further comprising:
creating a first time bubble between the first data burst and the third data burst; and
creating a second time bubble between the second data burst and the fourth data burst.

### Claim 13 (depends on 12)

The apparatus of claim 12, wherein the first time bubble and the second time bubble are associated with a register of a memory controller.

### Claim 14

A medium comprising instructions that when executed by a processor perform a method, the method comprising:
receiving a first data burst associated with a first data line;
receiving a second data burst associated with a second data line;
determining a first one or more stuff bits to be transmitted after the first data burst and a second one or more stuff bits to be transmitted after the second data burst based on an amount of interference reduction produced by a combination of the first one or more stuff bits and the second one or more stuff bits; and
outputting data comprising the first data burst, the first one or more stuff bits, the second data burst and the second one or more stuff bits.

### Claim 15 (depends on 14)

The medium of claim 14, wherein the determining the first one or more stuff bits and the second one or more stuff bits comprises:
determining an amount of interference reduction associated with each possible combination of the first one or more stuff bits and the second one or more stuff bits; and
determining a combination that produces less interference than remaining combinations of the first one or more stuff bits and the second one or more stuff bits.

### Claim 16 (depends on 15)

The medium of claim 15, wherein the determining of first one or more stuff bits and the second one or more stuff bits is further based on an amount of residual interference from a previous data burst.

### Claim 17 (depends on 14)

The medium of claim 14, further comprising:
receiving a third data burst associated with the first data line and a fourth data burst associated with the second data line.

### Claim 18 (depends on 17)

The medium of claim 17, further comprising:
creating a first time bubble between the first data burst and the third data burst; and
creating a second time bubble between the second data burst and the fourth data burst.

### Claim 19 (depends on 18)

The medium of claim 18, wherein the first time bubble and the second time bubble are associated with a register of a memory controller.