# US 2014/0156894 A1 · Msi events using dynamic memory monitoring > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0156894 A1 - Document ID: US20140156894A1 - Status: Published application - Kind: A1 - Application number: 13/689,950 - Filed: 2012-11-30 - Published: 2014-06-05 - Earliest claimed: 2012-11-30 - Assignees: Red Hat Israel, Ltd. - Applicants: Red Hat Israel, Ltd. - Inventors: Michael Tsirkin; Avi Kivity; Dor Laor - Web page: https://patentgrep.com/patent/US20140156894A1 ## CPC - G06F 13/24: using interrupt (G06F13/32 takes precedence) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A method and system for managing message-signaled interrupt-based events sent from an event source to a host or a guest is disclosed. A central processing unit instructs an event source to write a message-signaled interrupt to a designated address of a random access memory of the host. The host or a guest of the central processing unit executes a memory monitoring instruction to the designated address. The host or the guest enters a wait state. The host or the guest detects a write of the message-signaled interrupt by the event source to the designated address, the message-signaled interrupt comprising data items pertaining to an event to be performed. The host or the guest exits from the wait state. The host or the guest performs an atomic operation with respect to the event based on the data items in the message-signaled interrupt. ## Claims ### Claim 1 A computer-implemented method, comprising: instructing, by a central processing unit, an event source to write a message-signaled interrupt to a designated address of a random access memory of a host. ### Claim 2 (depends on 1) The method of claim 1, further comprising: executing a memory monitoring instruction to the designated address; entering a wait state; detecting a write of the message-signaled interrupt by the event source to the designated address, the message-signaled interrupt comprising data items pertaining to an event to be performed; exiting from the wait state; and performing an atomic operation with respect to the event based on the data items in the message-signaled interrupt. ### Claim 3 (depends on 2) The method of claim 2, wherein the method is performed by a guest associated with the host. ### Claim 4 (depends on 2) The method of claim 2, wherein the method is performed by the host. ### Claim 5 (depends on 1) The method of claim 1, wherein the designated address is in guest memory. ### Claim 6 (depends on 1) The method of claim 1, wherein the designated address is in host memory. ### Claim 7 (depends on 1) The method of claim 1, wherein instructing the event source to write the message-signaled interrupt to the designated address occurs prior to or following the execution of the memory monitoring to the designated address. ### Claim 8 (depends on 1) The method of claim 1, wherein message-signaled interrupt is an MSI interrupt or an MSI-X interrupt. ### Claim 9 (depends on 1) The method of claim 1, wherein the atomic operation comprises concurrently reading the designated address to detect the event and clearing the event. ### Claim 10 (depends on 9) The method of claim 9, wherein the atomic operation is one of a compare and exchange operation or a test and clear operation. ### Claim 11 (depends on 1) The method of claim 1, wherein, when a plurality of event sources raise corresponding events, selecting one set of event sources for writing the message-signaled interrupt to the designated address and selecting a remaining set of event sources for writing the message-signaled table directly to a programmable interrupt controller associated with the host. ### Claim 12 (depends on 11) The method of claim 11, wherein the selecting is based on measuring a frequency of detected events from the event source. ### Claim 13 (depends on 12) The method of claim 12, further comprising: mapping events received from the event source to the designated address when the measured frequency of detected events from the event source is equal to or above a frequency threshold and detecting events from an associated interrupt controller when the measured frequency of detected events from the event source is below the frequency threshold. ### Claim 14 (depends on 1) The method of claim 1, wherein the event source is a hardware device of a host or a virtual device of a guest. ### Claim 15 (depends on 1) The method of claim 1, wherein the event source is a PCI-based device. ### Claim 16 A non-transitory computer readable storage medium including instructions that, when executed by a central processing unit, cause the central processing unit to: instruct an event source to write a message-signaled interrupt to a designated address of a random access memory of a host. ### Claim 17 (depends on 16) The non-transitory computer readable storage medium of claim 16, further comprising: executing a memory monitoring instruction to the designated address; entering a wait state; detecting a write of the message-signaled interrupt by the event source to the designated address, the message-signaled interrupt comprising data items pertaining to an event to be performed; exiting from the wait state; and performing an atomic operation with respect to the event based on the data items in the message-signaled interrupt. ### Claim 18 (depends on 16) The non-transitory computer readable storage medium of claim 16, wherein, when a plurality of event sources raise corresponding events intended for processing by the central processing unit, the central processing unit selects one set of event sources for writing the message-signaled interrupt to the designated address and selects a remaining set of event sources for writing the message-signaled interrupt to a programmable interrupt controller associated with the central processing unit. ### Claim 19 A computer system comprising: a memory; a central processing unit, coupled to the memory, the central processing unit to: instruct an event source to write a message-signaled interrupt to a designated address of a random access memory of a host. ### Claim 20 (depends on 19) The system of claim 19, the central processing unit further to: execute a memory monitoring instruction to the designated address; enter a wait state; detect a write of the message-signaled interrupt by the event source to the designated address, the message-signaled interrupt comprising data items pertaining to an event to be performed; exit from the wait state; and perform an atomic operation with respect to the event based on the data items in the message-signaled interrupt.