# US 2014/0156893 A1 · Can bus edge timing control apparatus, systems and methods

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- Number: US 2014/0156893 A1
- Document ID: US20140156893A1
- Status: Published application
- Kind: A1
- Application number: 14/087,879
- Filed: 2013-11-22
- Published: 2014-06-05
- Earliest claimed: 2012-12-05
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Scott Allen Monroe; David Wayne Stout
- Web page: https://patentgrep.com/patent/US20140156893A1

## CPC

- G06F 13/372: using a time-dependent priority, e.g. individually loaded time counters or time slot
- G06F 13/3625: {using a time dependent access}
- G06F 13/364: using independent requests or grants, e.g. using separated request and grant lines
- G06F 13/4072: {Drivers or receivers (G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002)}
- H04L 2012/40215: {Controller Area Network CAN}
- H04L 2012/40273: {the transportation system being a vehicle}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

Structures and methods herein insert one or more parallel “recessive nulling” driver impedances across a controller area network (CAN) bus starting at the time of a dominant-to-recessive data bit transition and extending for a selected recessive nulling time period. Doing so increases a rate of decay of a CAN bus dominant-to-recessive differential signal waveform, permits a shortened recessive bit time period, and allows for increased CAN bus bandwidth. Various modes of operation are applicable to various CAN bus node topologies. Recessive nulling may be applied to only the beginning portion of a recessive bit following a dominant bit (“LRN mode”) or to the entire recessive bit time (“HRN mode”). And, some embodiments may apply LRN operations to some recessive CAN frame bits and HRN operations to others.

## Claims

### Claim 1

A method of controller area network (CAN) bus recessive transmit data (TxD) bit timing control, comprising:
detecting a dominant-to-recessive data bit transition in a CAN TxD frame generated by a CAN node controller; and
performing a recessive nulling operation by maintaining at least one recessive nulling driver impedance in parallel with a main CAN node physical layer (PHY) driver across the CAN bus starting at the time of the dominant-to-recessive data bit transition and extending for a selected recessive nulling time period in order to increase a rate of decay of a CAN bus dominant-to-recessive differential signal waveform.

### Claim 2 (depends on 1)

The method of CAN bus dominant-to-recessive TxD bit timing control of claim 1, a light recessive nulling (LRN) mode of the recessive nulling operation comprising:
terminating the recessive nulling operation by releasing the at least one recessive nulling driver impedance from the CAN bus upon expiration of the recessive nulling time period and prior to a bus state sampling time within a tbit associated with the recessive TxD bit to avoid bus loading that could interfere with a CAN bus arbitration process.

### Claim 3 (depends on 2)

The method of CAN bus dominant-to-recessive TxD bit timing control of claim 2, the LRN mode of the recessive nulling operation further comprising:
selecting the recessive nulling time period associated with the LRN operation as a function of an expected bus impedance during a recessive bus state, the expected bus impedance during the recessive bus state a function of at least one of CAN bus length, CAN bus distributed parasitic capacitance, or CAN bus loading contributed by a CAN node PHY driver, the recessive nulling time period selected to drive the CAN bus differential waveform toward a recessive state at a chosen rate.

### Claim 4 (depends on 3)

The method of CAN bus dominant-to-recessive TxD bit timing control of claim 3, the LRN mode of the recessive nulling operation further comprising:
performing the recessive nulling operation on each recessive bit following a dominant bit in the CAN TxD frame; and
increasing a rate of transmission of all recessive data bits in the CAN TxD frame as compared to a CAN standard rate of transmission.

### Claim 5 (depends on 1)

The method of CAN bus dominant-to-recessive TxD bit timing control of claim 1, a heavy recessive nulling (HRN) mode of the recessive nulling operation comprising:
extending the recessive nulling time period to include entire tbit periods of successive recessive bits in the CAN TxD frame.

### Claim 6 (depends on 5)

The method of CAN bus dominant-to-recessive TxD bit timing control of claim 5, the HRN mode of the recessive nulling operation to include at least two recessive nulling driver impedances in parallel with each other.

### Claim 7 (depends on 5)

The method of CAN bus dominant-to-recessive TxD bit timing control of claim 5, further comprising:
performing the recessive nulling operation in HRN mode on each recessive bit in the CAN transmit frame not subject to CAN bus arbitration and not subject to CAN bus contention caused by simultaneous transmission from two or more CAN bus nodes;
performing a light recessive nulling (LRN) operation on each recessive bit following a dominant bit subject to CAN bus arbitration or subject to CAN bus contention caused by simultaneous transmission from two or more CAN bus nodes; and
increasing a rate of transmission of all recessive data bits in the CAN transmit frame as compared to a CAN-standard rate of transmission.

### Claim 8 (depends on 5)

The method of CAN bus dominant-to-recessive TxD bit timing control of claim 5, further comprising:
for a point-to-point or point-to-multipoint CAN bus node topology with a single transmitting node, performing HRN mode recessive nulling operations on all recessive data bits in the CAN transmit frame; and
increasing a rate of transmission of all recessive data bits in the CAN transmit frame as compared to a CAN-standard rate of transmission.

### Claim 9

An apparatus for exercising controller area network (CAN) bus dominant-to-recessive transmit data (TxD) bit timing control, comprising:
a main CAN node physical layer (PHY) differential driver circuit to drive a CAN bus to an active state upon receipt of a dominant TxD bit in a CAN TxD frame received from a CAN node controller; and
at least one recessive nulling fractional differential driver circuit output-coupled to the main CAN node PHY differential driver circuit to enter a conductive state and insert a recessive nulling impedance in parallel with a differential output of the main CAN node PHY driver across the CAN bus for a selected recessive nulling time period during a recessive bit time period associated with at least one recessive data bit in the CAN TxD frame in order to increase a rate of decay of a CAN bus dominant-to-recessive differential signal waveform associated with a dominant-to-recessive data bit transition.

### Claim 10 (depends on 9)

The apparatus for exercising CAN bus dominant-to-recessive TxD bit timing control of claim 9, the main CAN PHY differential driver circuit further comprising:
a differential pre-driver to accept an active-LOW TxD input from a CAN node controller;
a PMOS transistor gate-coupled to an in-phase output of the differential pre-driver, a drain terminal of the PMOS transistor communicatively coupled to a voltage HIGH rail (CANH) of the CAN bus;
a first diode coupled in series with a current path of the PMOS transistor, a cathode terminal of the first diode coupled to a source terminal of the PMOS transistor and an anode terminal of the first diode coupled to a positive supply voltage rail;
an NMOS transistor gate-coupled to an out-of-phase output of the differential pre-driver, a source terminal of the NMOS transistor communicatively coupled to a ground voltage rail; and
a second diode coupled in series with a current path of the NMOS transistor, a cathode terminal of the second diode coupled to a drain terminal of the NMOS transistor and an anode terminal of the second diode coupled to a voltage LOW rail (CANL) of the CAN bus.

### Claim 11 (depends on 9)

The apparatus for exercising CAN bus dominant-to-recessive TxD bit timing control of claim 9, the recessive nulling fractional differential driver circuit further comprising:
a differential pre-driver to accept an active-LOW input from a dominant-to-recessive TxD bit timing control logic circuit;
a PMOS transistor gate-coupled to an in-phase output of the differential pre-driver, a drain terminal of the PMOS transistor communicatively coupled to a voltage HIGH rail (CANH) of the CAN bus;
a first diode coupled in series with a current path of the PMOS transistor, a cathode terminal of the first diode coupled to a source terminal of the PMOS transistor and an anode terminal of the first diode coupled to a common-mode voltage source;
an NMOS transistor gate-coupled to an out-of-phase output of the differential pre-driver, a source terminal of the NMOS transistor communicatively coupled to the common-mode voltage source; and
a second diode coupled in series with a current path of the NMOS transistor, a cathode terminal of the second diode coupled to a drain terminal of the NMOS transistor and an anode terminal of the second diode coupled to a voltage LOW rail (CANL) of the CAN bus.

### Claim 12 (depends on 9)

The apparatus for exercising CAN bus dominant-to-recessive TxD bit timing control of claim 9, further comprising:
a first timing control logic circuit to control a first recessive nulling fractional differential driver circuit, including:
an OR gate with an output coupled to the first recessive nulling fractional differential driver circuit to drive the fractional differential driver circuit to a conductive state when the OR gate output is logic LOW, a negated first input of the OR gate coupled to an dominant LOW TxD input line to ensure that a dominant LOW state of the TxD signal holds an output of the first fractional differential driver circuit in an inactive high impedance state;
an AND gate with an output coupled to a non-negated second input of the OR gate, a negated first input of the AND gate coupled to an active-HIGH flexible data rate (FD) indicator signal line to drive the first fractional differential driver circuit to the conductive state when the FD indicator signal is active during recessive TxD bit times; and
a delay line coupled between the TxD input line and a second input of the AND gate to cause the first fractional differential driver circuit to be driven to the conductive state at a TxD dominant-to-recessive transition for the selected recessive nulling time period and then to be released to the high impedance state at the end of the selected recessive nulling time period.

### Claim 13 (depends on 9)

The apparatus for exercising CAN bus dominant-to-recessive TxD bit timing control of claim 9, further comprising:
a second timing control logic circuit to control a second recessive nulling fractional differential driver circuit, including:
a NAND gate with an output coupled to an input of the second fractional differential driver circuit to drive the second fractional differential driver circuit to the conductive state when the NAND gate output is logic LOW, a first input of the NAND gate coupled to a TxD input line to insure that outputs of the second recessive nulling driver are held in a high impedance state during dominant TxD bit times, and a second input of the NAND gate coupled to an active-HIGH flexible data rate (FD) indicator signal input from the CAN controller to cause the second fractional differential driver circuit to be driven to the conductive state when the FD signal is set HIGH by the CAN controller and the TxD input line is HIGH during recessive TxD bit times.

### Claim 14 (depends on 9)

The apparatus for exercising CAN bus dominant-to-recessive TxD bit timing control of claim 9, further comprising:
a common-mode voltage supply element to supply a common-mode voltage rail to the at least one recessive nulling fractional differential driver circuit.

### Claim 15 (depends on 14)

The apparatus for exercising CAN bus dominant-to-recessive TxD bit timing control of claim 14, the common-mode voltage supply element an operational amplifier with a voltage level of V(CC)/2 applied to a non-inverting input and an output of the operational amplifier fed back to an inverting input.

### Claim 16

A system to exercise controller area network (CAN) bus dominant-to-recessive transmit data (TxD) bit timing control, comprising:
a CAN bus transceiver to send differential signals on a CAN bus and to exercise control of a CAN bus impedance;
a CAN bus node controller to assemble transmit data (TxD) frames for transmission to another bus node on the CAN bus and to selectively activate a flexible data rate (FD) signal line;
a main CAN node physical layer (PHY) differential driver portion of the CAN bus transceiver to drive the CAN bus to an active state upon receipt of a dominant TxD bit in a CAN TxD frame received from the CAN bus node controller; and
at least one recessive nulling fractional differential driver portion of the CAN bus transceiver output-coupled in parallel with the main CAN node PHY differential driver circuit to perform a recessive nulling operation by entering a conductive state and inserting a recessive nulling impedance in parallel with a differential output of the main CAN node PHY differential driver circuit across the CAN bus for a selected recessive nulling time period during a recessive bit time period associated with at least one recessive data bit in the CAN TxD frame in order to increase a rate of decay of a CAN bus dominant-to-recessive differential signal waveform associated with a dominant-to-recessive data bit transition.

### Claim 17 (depends on 16)

The system to exercise CAN bus dominant-to-recessive TxD bit timing control of claim 16, further comprising:
a node microcontroller communicatively coupled to the CAN bus node controller to generate messages to be transmitted to other node microcontrollers on the CAN bus.

### Claim 18 (depends on 16)

The system to exercise CAN bus dominant-to-recessive TxD bit timing control of claim 16, further comprising:
an FD logic module component of the CAN bus node controller to cause the CAN bus transceiver to insert an additional recessive nulling impedance across the CAN bus and to indicate a portion of the CAN frame to be transmitted at a higher than CAN-standard data rate.

### Claim 19 (depends on 16)

The system to exercise CAN bus dominant-to-recessive TxD bit timing control of claim 16, further comprising:
a dominant-to-recessive edge timing control element to determine the recessive nulling time period.

### Claim 20 (depends on 19)

The system to exercise CAN bus dominant-to-recessive TxD bit timing control of claim 19, the dominant-to-recessive edge timing control element being at least one of a resistor or a capacitor.