# US 2014/0156891 A1 · Systems and methods for automatically generating master-slave latch structures with fully registered flow control

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- Number: US 2014/0156891 A1
- Document ID: US20140156891A1
- Status: Published application
- Kind: A1
- Application number: 13/693,869
- Filed: 2012-12-04
- Published: 2014-06-05
- Earliest claimed: 2012-12-04
- Assignees: NVIDIA Corporation
- Inventors: Robert A. Alfieri
- Web page: https://patentgrep.com/patent/US20140156891A1

## CPC

- G06F 13/362: with centralised access control
- G06F 30/327: Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A method for automatically generating master-slave latch structures is disclosed. A method includes, from another logic synthesis system that invokes a logic synthesis system for generating master-slave latch structures, accessing high level design descriptions of a master-slave latch structure that indicate a fully registered flow control structure design and based on the high level design descriptions, generating a master-slave latch structure design to include at least one master-slave latch pair.

## Claims

### Claim 1

In a logic synthesis system for automatically generating master-slave latch structures, a computer implemented method for automatically generating master-slave latch structure designs, the method comprising:
from another logic synthesis system, that invokes said logic synthesis system for automatically generating master-slave latch structures, accessing high level design descriptions of a master-slave latch structure that indicate a fully registered flow control structure design; and
based on said high level design descriptions, automatically generating a master-slave latch structure design to comprise at least one master-slave latch pair.

### Claim 2 (depends on 1)

The method of claim 1 wherein said another logic synthesis system is one of a FIFO generator, a retiming flow and a plugin.

### Claim 3 (depends on 1)

The method of claim 1 further comprising automatically invoking said logic synthesis system to generate components of interface senders and receivers, registered read sides and sequential memories.

### Claim 4 (depends on 1)

The method of claim 1 wherein said logic synthesis system is invoked to generate an implicit retiming stage.

### Claim 5 (depends on 1)

The method of claim 1 wherein said logic synthesis system is invoked to generate an explicit retiming stage.

### Claim 6 (depends on 1)

The method of claim 1 wherein said master-slave latch structure design comprises a write data register.

### Claim 7 (depends on 1)

The method of claim 1 wherein said master-slave latch structure design comprises one of a single master-slave latch pair and N/2 rows of master-slave latches.

### Claim 8

In a logic synthesis platform, a computer implemented method for automatically generating a master-slave latch structure design, the method comprising:
receiving at a first logic synthesis system, high level design descriptions for a master-slave latch structure design that indicate a fully registered flow control structure design;
invoking from said first logic synthesis system, a second logic synthesis system based on a determination that fully registered flow control is involved;
accessing from said first logic synthesis system said high level design descriptions; and
based on said high level design descriptions, automatically generating said master-slave latch structure design that comprises at least one master-slave latch pair.

### Claim 9 (depends on 8)

The method of claim 8 wherein said first logic synthesis system is one of a FIFO generator, a retiming flow and a plugin.

### Claim 10 (depends on 8)

The method of claim 8 further comprising automatically invoking said second logic synthesis system to generate components of interface senders and receivers, registered read sides and sequential memories.

### Claim 11 (depends on 8)

The method of claim 8 wherein said second logic synthesis system is invoked to generate an implicit retiming stage.

### Claim 12 (depends on 8)

The method of claim 8 wherein said second logic synthesis system is invoked to generate an explicit retiming stage.

### Claim 13 (depends on 8)

The method of claim 8 wherein said master-slave latch structure design comprises a write data register and a 1-deep RAM.

### Claim 14 (depends on 8)

The method of claim 8 wherein said master-slave latch structure design comprises one of a single master-slave latch pair and N/2 rows of master-slave latch pairs.

### Claim 15

A computer system, comprising:
memory;
at least one processer; and
a display component,
wherein said at least one processer executes, a method for automatically generating a master-slave latch structure design, comprising:
receiving at a first logic synthesis system, high level design descriptions for said master-slave latch structure design that indicate a fully registered flow control structure design;
invoking from said first logic synthesis system, a second logic synthesis system based on a determination that fully registered flow control is involved;
accessing at said second logic synthesis system said high level design descriptions for said master-slave latch structure; and
based on said high level design descriptions, automatically generating said master-slave latch structure design that comprises at least one master-slave latch pair.

### Claim 16 (depends on 15)

The system of claim 15 wherein said first logic synthesis system is one of a FIFO generator, a retiming flow and a plugin.

### Claim 17 (depends on 15)

The system of claim 15 further comprising invoking said second logic synthesis system to generate components of interface senders and receivers, registered read sides and sequential memories.

### Claim 18 (depends on 15)

The system of claim 15 wherein said second logic synthesis system is invoked to generate an implicit retiming stage.

### Claim 19 (depends on 15)

The system of claim 15 wherein said second logic synthesis system is invoked to generate an explicit retiming stage.

### Claim 20 (depends on 15)

The system of claim 15 wherein said second logic synthesis system is invoked to generate an explicit retiming stage.