# US 2014/0156889 A1 · Apparatus and method for monitoring signals transmitted in bus

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- Number: US 2014/0156889 A1
- Document ID: US20140156889A1
- Status: Published application
- Kind: A1
- Application number: 13/945,103
- Filed: 2013-07-18
- Published: 2014-06-05
- Earliest claimed: 2012-12-04
- Assignees: Hon Hai Precision Industry Co., Ltd.; HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD.
- Applicants: Hon Hai Precision Industry Co., Ltd.; HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD
- Inventors: KANG-BIN WANG
- Web page: https://patentgrep.com/patent/US20140156889A1

## CPC

- G06F 13/385: {for adaptation of a particular data processing system to different peripheral devices}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A signal monitor includes a signal collecting unit, two registers, a processing unit, and a Universal Asynchronous Receiver/Transmitter (UART). The signal collecting unit collects real-time signals from a bus, converts the real-time signals into accessible data, and stores the accessible data in the two registers. The processing unit reads the accessible data from the two registers and determines status of the real-time signals by examining the accessible data in the reading. The UART asynchronously transmits the status of the real-time signals to a control terminal. A method for monitoring signals transmitted in a bus is also provided.

## Claims

### Claim 1

A signal monitor, comprising:
a signal collecting unit adapted to collect real-time signals from a bus, to convert the real-time signals into accessible data;
a first register and a second register adapted to store the accessible data;
a processing unit adapted to retrieve the accessible data from the first register and the second register, to determine status of the real-time signals by examining the accessible data; and
a Universal Asynchronous Receiver/Transmitter (UART) adapted to asynchronously transmit the status of the real-time signals to a control terminal.

### Claim 2 (depends on 1)

The signal monitor of claim 1, further comprising a first multiplexer, wherein the signal collecting unit is further adapted to transmit the accessible data to the first multiplexer, the first multiplexer is adapted to selectively store the accessible data in the first register and the second register.

### Claim 3 (depends on 2)

The signal monitor of claim 2, further comprising a second multiplexer, wherein the processing unit is further adapted to send a read command to the second multiplexer, the second multiplexer is adapted to selectively read the accessible data from the first register and the second register and to transmit the accessible data to the processing unit in response to the read command.

### Claim 4 (depends on 3)

The signal monitor of claim 3, further comprising a data Write/Read (W/R) controller, wherein when the first register is full, the data W/R controller is adapted to set the first register to a write-protected state, when the second register is full, the data W/R controller is adapted to set the second register to a write-protected state.

### Claim 5 (depends on 4)

The signal monitor of claim 4, wherein when the first register is in the write-protected state, the first multiplexer is adapted to store the accessible data in the second register, when the second register is in the write-protected state, the first multiplexer is adapted to store the accessible data in the first register, when both of the first and second registers are in the write-protected state, the first multiplexer is adapted to suspend the accessible data transmitted from the signal collecting unit.

### Claim 6 (depends on 5)

The signal monitor of claim 5, wherein when both of the first and second registers are in the write-protected state, the signal collecting unit is adapted to suspend collecting the real-time signals from the bus.

### Claim 7 (depends on 6)

The signal monitor of claim 6, wherein when the second multiplexer has finished reading the accessible data from the first register, the data W/R controller is adapted to set the first register to a write-permitted state, when the second multiplexer has finished reading the accessible data from the second register, the data W/R controller is adapted to set the second register to a write-permitted state.

### Claim 8 (depends on 1)

The signal monitor of claim 1, wherein each of the first and second registers is a First Input First Output (FIFO) register.

### Claim 9 (depends on 1)

The signal monitor of claim 1, further comprising an indicating lamp adapted to flicker while the processing unit is examining the accessible data.

### Claim 10 (depends on 1)

The signal monitor of claim 1, further comprising a wireless network interface adapted to establish a wireless connection with the control terminal and to transmit the status of the real-time signals to the control terminal via the wireless connection.

### Claim 11

A method for monitoring signals transmitted in a bus, the method comprising:
collecting real-time signals from a bus and converting the real-time signals into accessible data by a signal collecting unit;
storing the accessible data in a first register and a second register by a first multiplexer;
retrieving the accessible data from the first register and the second register and determining status of the real-time signals by examining the accessible data by a processing unit; and
asynchronously transmitting the status of the real-time signals to a control terminal by a UART.

### Claim 12 (depends on 11)

The method of claim 11, further comprising transmitting the accessible data to a first multiplexer by the signal collecting unit, wherein the first multiplexer selectively stores the accessible data in the first register and the second register.

### Claim 13 (depends on 12)

The method of claim 12, further comprising sending a read command to the second multiplexer by the processing unit, wherein the second multiplexer selectively reads the accessible data from the first register and the second register and transmits the accessible data to the processing unit in response to the read command.

### Claim 14 (depends on 13)

The method of claim 13, further comprising:
when the first register is full, setting the first register to a write-protected state by a data W/R controller; and
when the second register is full, setting the second register to a write-protected state by the data W/R controller.

### Claim 15 (depends on 14)

The method of claim 14, further comprising:
when the first register is in the write-protected state, storing the accessible data in the second register by the first multiplexer;
when the second register is in the write-protected state, storing the accessible data in the first register by the first multiplexer; and
when both of the first and second registers are in the write-protected state, suspending the accessible data transmitted from the signal collecting unit by the first multiplexer.

### Claim 16 (depends on 15)

The method of claim 15, further comprising suspending collecting the real-time signals from the bus when both of the first and second registers are in the write-protected state.

### Claim 17 (depends on 16)

The method of claim 16, further comprising:
when the second multiplexer has finished reading the accessible data from the first register, setting the first register to a write-permitted state by the data W/R controller; and
when the second multiplexer has finished reading the accessible data from the second register, setting the second register to a write-permitted state by the data W/R controller.

### Claim 18 (depends on 11)

The method of claim 11, wherein each of the first and second registers is an FIFO register.

### Claim 19 (depends on 11)

The method of claim 11, further comprising controlling an indicating lamp to flicker while the processing unit is examining the accessible data.

### Claim 20 (depends on 11)

The method of claim 11, further comprising establishing a wireless connection with the control terminal and transmitting the status of the real-time signals to the control terminal via the wireless connection by a wireless network interface.