# US 2014/0156880 A1 · Memory controller and operating method thereof

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- Number: US 2014/0156880 A1
- Document ID: US20140156880A1
- Status: Published application
- Kind: A1
- Application number: 14/095,177
- Filed: 2013-12-03
- Published: 2014-06-05
- Earliest claimed: 2012-12-03
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Hojun SHIM
- Web page: https://patentgrep.com/patent/US20140156880A1

## CPC

- G06F 3/061: {Improving I/O performance}
- G06F 3/0656: {Data buffering arrangements}
- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06F 13/1668: {Details of memory controller}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A memory controller is provided which includes a host interface configured to provide an interface for communication with a host; a buffer memory configured to store user data and metadata of the user data; and a DMA controller configured to access the buffer memory to check the metadata and to provide user data corresponding to a logical block address requested from a host to the host interface according to the checking result. The metadata includes status information of the user data stored at the buffer memory. Before providing the host interface with user data corresponding to a first logical block address requested from the host, the DMA controller checks metadata of user data corresponding to a second logical block address requested from the host.

## Claims

### Claim 1

A memory controller, comprising:
a host interface configured to provide an interface for communication with a host;
a buffer memory configured to store first and second user data and associated metadata, the metadata including status information of the associated one of the first and second user data; and
a DMA controller configured to,
receive a request from a host to retrieve the first user data at a first logical block address and the second user data at a second logical block address,
check the metadata associated with the first user data, and
provide the first user data to the host interface, based on a result of checking the metadata associated with the first user data, before or after simultaneously checking the metadata associated with the second user data.

### Claim 2 (depends on 1)

The memory controller of claim 1, wherein after providing the host interface with the first user data, the DMA controller is configured to provide the host interface with the metadata associated with the second user data.

### Claim 3 (depends on 1)

The memory controller of claim 1, wherein when the checking indicates that the second user data is valid, the DMA controller is configured to provide the second user data to the host interface.

### Claim 4 (depends on 1)

The memory controller of claim 1, wherein the metadata includes information indicating whether the associated one of the first and second user data is valid, Cycle Redundancy Check (CRC) information.

### Claim 5 (depends on 1)

The memory controller of claim 1, wherein the buffer memory is a volatile memory.

### Claim 6 (depends on 1)

The memory controller of claim 1, wherein the buffer memory includes a first buffer memory and a second buffer memory, the first buffer memory being a dynamic random access memory (DRAM) and the second buffer memory being a static random access memory (SRAM).

### Claim 7 (depends on 6)

The memory controller of claim 6, wherein the first and second user data are stored at the first buffer memory and the associated metadata is stored at the second buffer memory.

### Claim 8 (depends on 1)

The memory controller of claim 1, wherein the host interface is a Peripheral Component Interconnect Express (PCIe) interface.

### Claim 9

A method of operating a memory controller, the method comprising:
receiving a read request for first user data corresponding to a first logical block address from a host;
receiving a read request for second user data corresponding to a second logical block address from the host;
checking metadata associated with the first user data;
checking metadata associated with the second user data;
transferring the first user data to the host; and
transferring the second user data to the host.

### Claim 10 (depends on 9)

The method of claim 9, wherein the read request for the first user data and the read request for the second user data are received at the same time.

### Claim 11 (depends on 9)

The method of claim 9, wherein the receiving the read request for the second user data is performed after the checking the metadata associated with the first user data.

### Claim 12 (depends on 9)

The method of claim 9, further comprising:
determining whether the first user data is valid after checking the metadata associated with the first user data.

### Claim 13 (depends on 9)

The method of claim 9, further comprising:
determining whether the second user data is valid after checking the metadata associated with the second user data.

### Claim 14 (depends on 9)

The method of claim 9, wherein the transferring the first user data and the transferring the second user data to the host is performed using a PCIe interface.

### Claim 15 (depends on 9)

The method of claim 9, wherein the metadata includes information indicating whether the associated user data is valid, Cycle Redundancy Check (CRC) information.

### Claim 16

A memory controller comprising:
a buffer memory configured to store user data and associated metadata therein, the metadata indicating whether the associated user data is corrupted;
a memory controller configured to,
receive a request from a host for a plurality of the user data;
determine if each of the plurality of user data in the request is corrupted based on the associated metadata prior to or simultaneously with transferring a first user data of the plurality of user data to the host.

### Claim 17 (depends on 16)

The memory controller of claim 16, wherein the memory controller is configured to determine if the plurality of user data is corrupted by,
checking the metadata associated with the first user data, and
checking the metadata associated with a second user data of the plurality of user data, and
the memory controller is further configured to transfer the first user data to the host after or simultaneously with the checking of the metadata associated with the second user data.

### Claim 18 (depends on 16)

The memory controller of claim 16, wherein the memory controller determines whether each of the plurality of user data in the request is corrupted by reading a validity bit of associated metadata stored in the buffer memory.

### Claim 19 (depends on 16)

The memory controller of claim 16, further comprising:
a host interface configured to send the requested plurality of user data whose associated metadata has been checked by the memory controller to the host.

### Claim 20 (depends on 16)

A storage device comprising:
the memory controller of claim 16; and
a nonvolatile memory configure to provide the user data to the buffer memory via a bus.