# US 2014/0156872 A1 · Secure element system integrated hard macro > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0156872 A1 - Document ID: US20140156872A1 - Status: Published application - Kind: A1 - Application number: 13/728,875 - Filed: 2012-12-27 - Published: 2014-06-05 - Earliest claimed: 2012-12-05 - Assignees: Broadcom Corporation - Applicants: Broadcom Corporation - Inventors: Mark Buer; Theodore Trost; Jacob Mendel - Web page: https://patentgrep.com/patent/US20140156872A1 ## CPC - G06F 21/53: by executing in a restricted environment, e.g. sandbox or secure virtual machine - G06F 12/1408: {by using cryptography (for digital transmission H04L9/00)} - G06F 13/16: for access to memory bus (G06F13/28 takes precedence) - G06F 13/4068: {Electrical coupling} - G06F 13/4282: {on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247)} - G06F 21/602: {Providing cryptographic facilities or services} - G06F 21/76: in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD] - G06F 2212/1052: Security improvement - G06F 2221/034: Test or assess a computer or a system - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract Systems and methods are provided that allow a secure processing system (SPS) to be implemented as a hard macro, thereby isolating the SPS from a peripheral processing system (PPS). The SPS and the PPS, combination, may form a secure element that can be used in conjunction with a host device and a connectivity device to allow the host device to engage in secure transactions, such as mobile payment over a near field communications (NFC) connection. As a result of the SPS being implemented as a hard macro isolated from the PPS, the SPS may be certified once, and re-used in other host devices without necessitating re-certification. ## Claims ### Claim 1 A system, comprising: a secure processing sub-system for at least one of storing secure data, storing target of evaluation (TOE) security functions data, and providing a platform on which secure application software is loaded, the secure processing sub-system comprising in part, an isolation bridge; and a peripheral processing sub-system for relaying communications to and from the secure processing sub-system, the peripheral processing system comprising at least one physical transport interface utilized for the relaying of the communications to and from the secure processing sub-system, wherein the secure processing sub-system is hardware isolated from the peripheral processing sub-system. ### Claim 2 (depends on 1) The system of claim 1, wherein the secure processing sub-system further comprises an isolation bridge for communicating with the peripheral processing sub-system while maintaining the hardware isolation from the peripheral processing sub-system. ### Claim 3 (depends on 2) The system of claim 2, wherein the isolation bridge comprises at least one of general purpose input/output pins, memory buffers, and mailboxes. ### Claim 4 (depends on 1) The system of claim 1, wherein the secure processing sub-system further comprises a low speed peripheral module including a secure clock domain, the secure clock domain being isolated and asynchronous from a clock generation module of the peripheral processing sub-system. ### Claim 5 (depends on 1) The system of claim 1, wherein the physical transport interface comprises at least one of an inter-integrated circuit interface (I2C), a serial peripheral interface (SPI), and a universal asynchronous receiver/transmitter (UART) interface. ### Claim 6 (depends on 1) The system of claim 1, wherein the secure processing sub-system utilizes both local flash memory dedicated to the secure processing sub-system and accessed via the first peripheral interface, and host device flash memory accessed through the peripheral processing system via one of a single wire protocol (SWP) interface and a dual wire protocol (DWP) interface. ### Claim 7 (depends on 1) The system of claim 1, wherein unique keys stored by the system protect the local flash memory and the host device flash memory. ### Claim 8 (depends on 1) The system of claim 1 further comprising, a connectivity device for providing communications capability to a host device, the connectivity device comprising at least a near field communications (NFC) controller, a Bluetooth controller, a wireless local area network (WLAN) controller, a cellular communications controller, and a global positioning satellite (GPS) controller. ### Claim 9 (depends on 7) The system of claim 7, wherein the peripheral processing sub-system mimics the NFC controller for the secure processing sub-system. ### Claim 10 (depends on 7) The system of claim 7, wherein the secure application software supports secure financial transactions involving the host device through at least one of NFC and direct transaction media. ### Claim 11 (depends on 1) The system of claim 1, wherein the secure processing sub-system further comprises an encrypted bus matrix over which communications within the secure processing sub-system occur. ### Claim 12 (depends on 1) The system of claim 1, wherein the secure processing sub-system is configured to communicate with a host device, and wherein the relaying of the communications to and from the secure processing sub-system occurs between the host device and the secure processing sub-system ### Claim 13 A system, comprising: a host device comprising a host processor and a first flash memory unit; a secure processing sub-system for at least one of storing secure data, storing target of evaluation (TOE) security functions data, and providing a platform on which secure application software is loaded, the secure processing sub-system comprising an isolation bridge and implemented as a hard macro; a peripheral processing sub-system for relaying communications to and from the secure processing sub-system and the host device, wherein the secure processing sub-system is hardware isolated from the peripheral processing sub-system; a connectivity device for providing communication capabilities for the host device; and a plurality of interfaces comprising: at least one physical transport slave interface within the peripheral processing sub-system for the relaying of the communications to and from the secure processing sub-system and the host processor; one of a single wire protocol (SWP) or a dual wire protocol (DWP) interface for accessing the first flash memory unit; and at least a physical transport master interface within the secure processing sub-system for accessing a second flash memory unit dedicated to the secure processing sub-system. ### Claim 14 (depends on 13) The system of claim 13, wherein the physical transport slave interface comprises at least one of an inter-integrated circuit interface (I2C), a serial peripheral slave interface (SPI), and a universal asynchronous receiver/transmitter (UART) interface, and wherein the physical transport master interface comprises a master SPI. ### Claim 15 (depends on 1) The system of claim 1, wherein the connectivity device comprises a near field communications (NFC) controller and at least one of a Bluetooth controller, a wireless local area network (WLAN) controller, a cellular communications controller, and a global positioning satellite (GPS) controller. ### Claim 16 (depends on 15) The system of claim 15, wherein the one of the SWP or the DWP interface is further configured to provide access to the NFC controller and the at least one of the Bluetooth controller, the WLAN controller, the cellular communications controller, and the GPS controller. ### Claim 17 A secure processing system, comprising: a secure processor; a memory block operatively connected to the secure processor for storing secure data, storing target of evaluation (TOE) security functions data, and providing a platform on which secure application software is loaded; a serial peripheral interface for communicating with a dedicated external flash memory unit; and an isolation bridge for communicating with external devices, wherein utilization of the isolation bridge effectuates a target of evaluation (TOE) boundary isolating the system from the external devices. ### Claim 18 (depends on 17) The secure processing system of claim 17, wherein the external devices comprise a host device, a connectivity device, and a peripheral processing system, and wherein the peripheral processing system and the secure processing in combination form an embedded secure element utilized in conjunction with the connectivity device and the host device for executing secure applications. ### Claim 19 (depends on 18) The secure processing system of claim 18 further comprising a low speed peripheral module including a secure clock domain, the secure clock domain being isolated and asynchronous from a clock generation module of the peripheral processing sub-system. ### Claim 20 (depends on 18) The secure processing system of claim 18, wherein the peripheral processing system comprises at least one physical transport interface enabling communications between the host device and the secure processing system via the isolation bridge.