# US 2014/0156253 A1 · Functional built-in self test for a chip > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0156253 A1 - Document ID: US20140156253A1 - Status: Published application - Kind: A1 - Application number: 13/693,236 - Filed: 2012-12-04 - Published: 2014-06-05 - Earliest claimed: 2012-12-04 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Kevin M. McIlvain; Robert B. Tremaine; Gary Van Huben - Web page: https://patentgrep.com/patent/US20140156253A1 ## CPC - G06F 11/27: Built-in tests - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract According to one embodiment, a self-test system integrated on a chip is provided, the chip including a functional logic module for performing a selected application. The self-test system includes a primary interface a primary interface to the functional logic module, the primary interface configured to interface with a primary device, an input interface protocol generator for generating a pattern to be inserted into the primary interface and a secondary interface to the functional logic module, the secondary interface configured to interface with a secondary device. The system also includes an emulator engine coupled to the secondary interface, the emulator engine for testing a function of the functional logic module based on the inserted patterns, the function being configured to communicate with a secondary device coupled to the secondary interface, wherein the emulator engine tests the function when no secondary device is coupled to the chip. ## Claims ### Claim 1 A self-test system integrated on a chip, the chip comprising a functional logic module for performing a selected application, the self-test system comprising: a primary interface to the functional logic module, the primary interface configured to interface with a primary device; an input interface protocol generator for generating a pattern to be inserted into the primary interface; a secondary interface to the functional logic module, the secondary interface configured to interface with a secondary device; an emulator engine coupled to the secondary interface, the emulator engine for testing a function of the functional logic module based on the inserted patterns, the function being configured to communicate with the secondary device, wherein the emulator engine tests the function when the secondary device is not coupled to the chip; an emulator checker in the emulator engine configured to determine that an input received by the emulator engine from the secondary interface is correct, the input generated by the functional logic module based on the inserted patterns, wherein the emulator engine is further configured to generate an output to the functional logic module based on the input and the testing of the function; and an output interface protocol payload checker coupled to the primary interface for determining that a response received from the primary interface is correct by comparing the response to an expected result, the response provided by the functional logic module based on the output generated by the emulator engine. ### Claim 2 (depends on 1) The system of claim 1, wherein the emulator engine, the input interface protocol generator and the output interface protocol payload checker enable the functional logic module to execute the inserted patterns at a maximum operational frequency. ### Claim 3 (depends on 1) The system of claim 1, wherein the function to communicate with the secondary device comprises a function to be used with a dynamic random-access memory (DRAM) device, the function further comprising at least one of: a read function, a write function, a refresh function and a calibration function. ### Claim 4 (depends on 1) The system of claim 1, wherein the primary interface is configured to interface with at least one selected from the group consisting of: a cache unit, a processing unit, a graphics controller, an I/O controller, a memory controller, a redundant array of independent disks (RAID) controller, a Peripheral Component Interconnect Express (PCIe) device and a network adapter. ### Claim 5 (depends on 1) The system of claim 1, further comprising a control unit configured to: maintain coherency for communications of the primary interface divided into multiple parallel execution streams; maintain coherency between communications of the primary interface and the primary functional logic; select at least one of the patterns to be inserted; control duration of operation of the self-test system; and enable the input interface protocol generator and output interface protocol payload checker to operate independently of the emulator engine while maintaining coherency. ### Claim 6 (depends on 5) The system of claim 5, further comprising a user-interface for receiving a test configuration for operating the control unit and for receiving user-direction for operating the self-test system. ### Claim 7 (depends on 1) The system of claim 1, wherein the emulator engine tests execution timing of the function to be used with the secondary device. ### Claim 8 (depends on 1) The system of claim 1, wherein the function to be used with the secondary device comprise a function to be used with one selected from the group consisting of: a Peripheral Component Interconnect Express (PCIe) device, a random access memory (RAM) device, a flash memory device, a universal serial bus (USB) and a sensor. ### Claim 9 (depends on 1) The system of claim 1, wherein the input interface protocol generator is further configured to generate a plurality of commands, wherein the functional logic module arbitrates placement of each of the plurality of commands for execution of the plurality of commands in parallel. ### Claim 10 (depends on 1) The system of claim 1, wherein test control logic, the input interface protocol generator, output interface protocol payload checker, emulator engine and emulator checker are configured to test: the functional logic module with no secondary devices coupled to the secondary interface and no primary devices coupled to the primary interface; the functional logic module with a secondary device coupled to the secondary interface and no primary devices coupled to the primary interface; the functional logic module with no secondary devices coupled to the secondary interface and a primary device coupled to the primary interface; and the functional logic module with a secondary device coupled to the secondary interface and a primary device coupled to the primary interface. ### Claim 11 (depends on 1) The system of claim 1, further comprising: a signature unit on the primary interface for generating a signature when sending communications to the functional logic module and when receiving data from the functional logic module; and a signature generator on the emulator engine, wherein the signature generator generates a signature for communications inbound from the functional logic module to the emulator engine and for communications outbound to the functional logic module from the emulator engine. ### Claim 12 A method for self-testing a functional logic module on a chip, the functional logic module for performing a selected application, the chip comprising a primary interface for the functional logic module, a secondary interface for the functional logic module, an input interface protocol generator coupled to the primary interface, an output interface protocol payload checker coupled to the primary interface and an emulator engine coupled to the secondary interface, the method comprising: generating, by the input interface protocol generator, patterns to be inserted into the primary interface, wherein the patterns are configured to test a function of the functional logic module that utilize the secondary interface; executing, by the functional logic module, the patterns inserted into the primary interface; receiving, by the emulator engine, an output from the secondary interface based on the inserted patterns executed by the functional logic module; determining that the output received by the emulator engine from the secondary interface is correct; transmitting test communications from the emulator engine to the functional logic module via the secondary interface, the test communications being transmitted based on the output received by the emulator engine, the emulator engine allowing testing of the function when a secondary device is not coupled to the secondary interface of the functional logic module; generating, by the functional logic module, a response based on the test communications received by the functional logic module, wherein the response is provided to the primary interface; and determining, by the output interface protocol payload checker, that the response is correct by comparing the response to an expected result. ### Claim 13 (depends on 12) The method of claim 12, wherein the emulator engine, the input interface protocol generator and the output interface protocol payload checker enable the functional logic module to execute the inserted patterns at a maximum operational frequency. ### Claim 14 (depends on 12) The method of claim 12, wherein receiving the output from the secondary interface further comprises receiving an output to test a secondary device function of the functional logic module, the secondary device function comprising at least one of: a read function, a write function, a refresh function and a calibration function. ### Claim 15 (depends on 12) The method of claim 12, wherein generating patterns to be inserted into the primary interface further comprises generating patterns to be inserted into at least one selected from the group consisting of: a cache unit, a processing unit, a graphics controller, an I/O controller, a memory controller, a RAID controller, a Peripheral Component Interconnect Express (PCIe) device and a network adapter. ### Claim 16 (depends on 12) The method of claim 12, further comprising: maintaining coherency for communications of the primary interface divided into multiple parallel execution streams; maintaining coherency between communications of the primary interface and the primary functional logic; select at least one of the patterns to be inserted; control duration of operation of the self-test system; and enable the input interface protocol generator and output interface protocol payload checker to operate independently of the emulator engine while maintaining coherency. ### Claim 17 (depends on 12) The method of claim 12, further comprising testing execution timing of the function of the functional logic module to be used with the secondary device. ### Claim 18 (depends on 12) The method of claim 12, wherein generating patterns to be inserted into the primary interface further comprises generating a plurality of commands, wherein the functional logic module arbitrates placement of each of the plurality of commands for execution of the plurality of commands in parallel. ### Claim 19 A self-test system integrated on a chip, the chip comprising a functional logic module for performing a selected application, the self-test system comprising: a primary interface to the functional logic module, the primary interface configured to interface with a primary device; an input interface protocol generator for generating commands to be inserted into the primary interface, wherein the functional logic module arbitrates placement of each of the commands for execution of the commands in parallel; a secondary interface to the functional logic module, the primary interface configured to interface with a secondary device, the functional logic module generating an input for the secondary interface based on the commands; an emulator engine coupled to the secondary interface, the emulator engine configured to test a function of the functional logic module based on the input received from the secondary interface, wherein the emulator engine is further configured to test the function when the secondary device is not coupled to the chip and wherein the emulator engine provides an output to the secondary interface based on testing of the function; and an output interface protocol payload checker coupled to the primary interface for determining that a response received from the primary interface is correct by comparing the response to an expected result, the response provided by the functional logic module based on the output received generated by the emulator engine, wherein the emulator engine, the input interface protocol generator and the output interface protocol payload checker enable the functional logic module to execute the inserted patterns at a maximum operational frequency. ### Claim 20 (depends on 19) The system of claim 19, wherein test control logic, the input interface protocol generator, output interface protocol payload checker, emulator engine and emulator checker are configured to test: the functional logic module with no secondary devices coupled to the secondary interface and no primary devices coupled to the primary interface; the functional logic module with a secondary device coupled to the secondary interface and no primary devices coupled to the primary interface; the functional logic module with no secondary devices coupled to the secondary interface and a primary device coupled to the primary interface; and the functional logic module with a secondary device coupled to the secondary interface and a primary device coupled to the primary interface.