# US 2014/0155012 A1 · Method and Apparatus for Efficient DC Calibration in a Direct-Conversion System with Variable DC Gain

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- Number: US 2014/0155012 A1
- Document ID: US20140155012A1
- Status: Published application
- Kind: A1
- Application number: 13/908,641
- Filed: 2013-06-03
- Published: 2014-06-05
- Earliest claimed: 2007-10-03
- Assignees: MaxLinear, Inc.
- Applicants: Maxlinear, Inc.
- Inventors: Curtis Ling; Andy Lo; Tete Sedalo
- Web page: https://patentgrep.com/patent/US20140155012A1

## CPC

- H04B 1/16: Circuits
- H04B 1/40: Circuits
- H04B: TRANSMISSION

## Abstract

A wireless communication receiver includes a multitude of look-up tables each storing a multitude of DC offset values associated with the gains of an amplification stage disposed in the wireless communication receiver. The entries for each look-up table are estimated during a stage of the calibration phase. During such a calibration stage, for each selected gain of an amplification stage, a search logic estimates a current DC offset number and compares it to a previous DC offset estimate that is fed back to the search logic. If the difference between the current and previous estimates is less than a predefined threshold value, the current estimate is treated as being associated with the DC offset of the selected gain of the amplification stage and is stored in the look-up table. This process is repeated for each selected gain of each amplification stage of interest until the look-up tables are populated.

## Claims

### Claim 1

A direct conversion receiver comprising:
a first look-up table configured to store a first plurality of DC offset values each being associated with a different one of a first plurality of gains of a first amplification stage; and
a second look-up table configured to store a second plurality of DC offset values each being associated with a different one of a second plurality of gains of a second amplification stage.

### Claim 2 (depends on 1)

The direct conversion receiver of claim 1 further comprising:
an analog-to-digital converter (ADC);
a search logic responsive to the ADC and configured to estimate a current DC offset value in accordance with a first selected gain of the first amplification stage and further in accordance with a feedback signal representing a DC offset value estimated by the search logic during a previous estimation iteration; and
a feedback loop responsive to the search logic and configured to supply the DC offset value estimated by the search logic during the previous iteration, said search logic further configured to store the current estimate of the DC offset value in the first look-up table if a difference between the current estimate of the DC offset value and the previous estimate of the DC offset value is smaller than a predefined threshold value.

### Claim 3 (depends on 2)

The direct conversion receiver of claim 2 wherein said search logic is further configured to estimate a second DC offset value in accordance with a first selected gain of the second amplification stage and further in accordance with a feedback signal representing an estimate of the second DC offset made during a previous estimation iteration, said search logic further configured to store the second estimate of the DC offset value in the second look-up table if a difference between a current second estimate of the DC offset value and a previous estimate of the second DC offset value is smaller than the predefined threshold value.

### Claim 4 (depends on 3)

The direct conversion receiver of claim 3 further comprising:
a first conversion block configured to convert each retrieved entry of the first look-up table to an associated 2's complement representation;
a second conversion block configured to convert each retrieved entry of the second look-up table to an associated 2's complement representation; and
a adder configured outputs of the first and second conversion blocks.

### Claim 5 (depends on 4)

The direct conversion receiver of claim 4 further comprising:
a saturation logic block adapted to saturate an output of the adder.

### Claim 6 (depends on 5)

The direct conversion block of claim 5 further comprising:
a third conversion block adapted to convert an output of the saturation logic block to an unsigned binary number.

### Claim 7 (depends on 6)

The direct conversion block of claim 6 further comprising:
a digital-to-analog converter (DAC) responsive to the third conversion block.

### Claim 8 (depends on 7)

The direct conversion block of claim 7 further comprising:
a filter responsive to the (DAC).

### Claim 9 (depends on 8)

The direct conversion block of claim 8 further comprising:
a delay element responsive to the ADC.

### Claim 10 (depends on 9)

The direct conversion block of claim 9 further comprising:
a third amplification stage coupled to an input of the first amplification stage; and
a frequency conversion module coupled to an output of the first amplification stage.

### Claim 11

A method of estimating a DC offset in a direct conversion receiver, the method comprising:
storing a first plurality of DC offset values each associated with a different one of a first plurality of gains of a first amplification stage; and
storing a second plurality of DC offset values each associated with a different one of a second plurality of gains of a second amplification stage.

### Claim 12 (depends on 11)

The method of claim 11 further comprising:
estimating a second DC offset value in accordance with a first selected gain of the first amplification stage and further in accordance with a feedback signal representing a first estimated DC offset value estimated during a first estimation iteration;
storing the second estimated DC offset in a first look-up table value if a difference between the second estimated DC offset value and the first estimated DC offset value is smaller than a predefined threshold value; and
estimating a third DC offset value if the difference between the second estimated DC offset value and the first estimated DC offset value is equal to or greater than the predefined threshold value.

### Claim 13 (depends on 12)

The method of claim 12 further comprising:
estimating a fifth DC offset value in accordance with a first selected gain of the second amplification stage and further in accordance with a feedback signal representing a fourth estimated DC offset value estimated during a first estimation iteration;
storing the fifth estimated DC offset value in a second look-up table if a difference between the fifth estimated DC offset value and the fourth estimated DC offset value is smaller than the predefined threshold value; and
estimating a sixth DC offset value if the difference between the fifth estimated DC offset value and the fourth estimated DC offset value is equal to or greater than the predefined threshold value.

### Claim 14 (depends on 13)

The method of claim 13 further comprising:
converting each stored entry of the first look-up table to an associated 2's complement representation;
converting each stored entry of the second look-up table to an associated 2's complement representation; and
adding the 2's complement representations of the entries stored in the first and second look-up tables to generate a sum.

### Claim 15 (depends on 14)

The direct conversion receiver of claim 14 further comprising:
saturating the sum.

### Claim 16 (depends on 15)

The direct conversion block of claim 15 further comprising:
converting the saturated sum to an unsigned binary number.

### Claim 17 (depends on 16)

The direct conversion block of claim 16 further comprising:
converting the unsigned binary number to a analog signal.

### Claim 18 (depends on 17)

The direct conversion block of claim 17 further comprising:
filtering the analog signal.

### Claim 19 (depends on 18)

The direct conversion block of claim 18 further comprising:
amplifying the analog signal using the second amplification stage;
converting the amplified signal to a digital signal; and
delaying the digital signal.

### Claim 20 (depends on 19)

The direct conversion block of claim 19 further comprising:
amplifying the signal before it is supplied to the first amplification stage; and
frequency converting the output of the first amplification stage.