# US 2014/0154881 A1 · Method of manufacturing metal silicide and semiconductor structure using the same

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- Number: US 2014/0154881 A1
- Document ID: US20140154881A1
- Status: Published application
- Kind: A1
- Application number: 14/174,931
- Filed: 2014-02-07
- Published: 2014-06-05
- Earliest claimed: 2012-03-07
- Assignees: Macronix International Co., Ltd.
- Applicants: Macronix International Co., Ltd.
- Inventors: Yen-Hao Shih; Ying-Tso Chen; Shih-Chang Tsai; Chun-Fu Chen
- Web page: https://patentgrep.com/patent/US20140154881A1

## CPC

- H10P 14/40: of conductive or resistive materials
- H10B 99/22: {including field-effect components}
- H10D 64/0131: {the additional conductive layer comprising a silicide layer formed by the silicidation reaction between the layer of silicon with a metal layer which is not formed by metal implantation}
- H10D 64/01326: {Aspects related to lithography, isolation or planarisation of the conductor}
- H10D 64/663: {the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates}
- H10D 84/0137: {the gate conductors being silicided}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method of manufacturing a metal silicide is disclosed below. A substrate having a first region and a second region is provided. A silicon layer is formed on the substrate. A planarization process is performed to make the silicon layer having a planar surface. A part of the silicon layer is removed to form a plurality of first gates on the first region and to form a plurality of second gates on the second region. The height of the first gates is greater than the height of the second gates, and top surfaces of the first gates and the second gates have the same height level. A dielectric layer covering the first gates and the second gates is formed and exposes the top surfaces of the first gates and the second gates. A metal silicide is formed on the top surfaces of the first gates and the second gates.

## Claims

### Claim 1

A method of manufacturing a semiconductor device, comprising:
providing a substrate, the substrate has a first region and a second region;
forming a silicon layer on the substrate;
performing a planarization process to make the silicon layer having a planar surface;
removing a part of the silicon layer to form a plurality of first gates on the first region and to form a plurality of second gates on the second region, the height of the first gates is greater than that of the second gates, and top surfaces of the first gates and the second gates have the same height level;
forming a dielectric layer on the substrate, the dielectric layer covers the first gates and the second gates and exposes the top surfaces of the first gates and the second gates; and
forming a metal silicide on the top surfaces of the first gates and the second gates.

### Claim 2 (depends on 1)

The method according to claim 1, wherein the first region is a cell array region, the second region is a periphery circuit region.

### Claim 3 (depends on 1)

The method according to claim 1, wherein the first region is a periphery circuit region, the second region is a cell array region.

### Claim 4 (depends on 1)

The method according to claim 1, wherein the substrate has an oblique surface on a local interconnection region between the first region and the second region.

### Claim 5 (depends on 1)

The method according to claim 1, wherein the first region has a difference in height with respect to the second region.

### Claim 6 (depends on 1)

The method according to claim 1, wherein the first gates are formed on the first region having a lower height level, and the second gates are formed on the second region having a higher height level.

### Claim 7 (depends on 1)

The method according to claim 1, wherein the steps of forming the silicide layer and the planarization process includes:
forming a poly silicon layer on the substrate;
forming an amorphous silicon layer on the poly silicon layer; and
planarizing the amorphous silicon layer, so that the amorphous layer aligns with the poly silicon layer and both of the amorphous silicon layer and the poly silicon layer have a planar surface.

### Claim 8 (depends on 7)

The method according to claim 7, after planarizing the amorphous silicon layer, further comprising heating the amorphous silicon layer to a recrystallization temperature and transforming the amorphous silicon layer into another poly silicon layer.

### Claim 9 (depends on 1)

The method according to claim 1, after forming the dielectric layer, further comprising planarizing the dielectric layer.

### Claim 10 (depends on 1)

The method according to claim 1, wherein the step of forming the metal silicide comprises:
forming a metal layer on the silicon layer and the dielectric layer;
conducting a thermal process, so that the metal layer reacts with the silicon layer to form the metal silicide; and
removing the remaining metal layer which is not reacted with the silicon layer.