# US 2014/0154878 A1 · Nor flash device manufacturing method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0154878 A1 - Document ID: US20140154878A1 - Status: Published application - Kind: A1 - Application number: 14/130,460 - Filed: 2012-07-31 - Published: 2014-06-05 - Earliest claimed: 2011-08-10 - Assignees: Csmc Technologies Fab2 Co., Ltd. - Inventors: Yawei Chen; Zhihon Jian - Web page: https://patentgrep.com/patent/US20140154878A1 ## CPC - H10P 50/00: Etching of wafers, substrates or parts of devices - H10B 41/30: characterised by the memory core region - H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures} - H10P 50/71: {using masks for conductive or resistive materials} - H10P 70/23: {during, before or after processing of insulating materials} - H10P 70/273: {the processing being a delineation of conductive layers, e.g. by RIE} - H10D 64/01326: {Aspects related to lithography, isolation or planarisation of the conductor} - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10B: ELECTRONIC MEMORY DEVICES - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract An embodiment of a NOR Flash device manufacturing method is disclosed, which includes: providing a substrate having a first polycrystalline silicon layer disposed thereon; forming a first hard mask layer on the first polycrystalline silicon layer; etching the first hard mask layer to form a first opening, and cleaning a gas pipeline connected to an etching cavity before etching the first hard mask layer; forming a second hard mask layer on the first hard mask layer, and the second hard mask layer covers the bottom and side wall of the first opening; etching the second hard mask layer to form a second opening, the width of the second opening is smaller than the width of the first opening; etching the first polycrystalline silicon, forming a floating gate. The NOR Flash device manufacturing method of the present invention improves the yield of the NOR Flash device. ## Claims ### Claim 1 A method of manufacturing a NOR Flash device, comprising: providing a substrate having a first polycrystalline silicon layer disposed thereon; forming a first hard mask layer on the first polycrystalline silicon layer; etching the first hard mask layer to form a first opening using a dry etching process, and cleaning a gas pipeline connected to an etching cavity prior to etching the first hard mask layer; forming a second hard mask layer on the first hard mask layer, wherein the second hard mask layer covers a bottom and a side wall of the first opening; etching the second hard mask layer to form a second opening using a self-aligning process, wherein a width of the second opening is smaller than a width of the first opening; and etching the first polycrystalline silicon layer to form a floating gate using the self-aligning process. ### Claim 2 (depends on 1) The method according to claim 1, wherein cleaning the gas pipeline connected to the etching cavity prior to etching the first hard mask layer comprises: cleaning a gas pipeline containing CO connected to the etching cavity. ### Claim 3 (depends on 1) The method according to claim 1, wherein etching the first hard mask layer to form the first opening using the dry etching process comprises: spin coating a photoresist layer on the hard mask layer; exposing the photoresist layer using a mask having a first opening pattern, then developing, and forming a photoresist layer having the first opening pattern, the first opening pattern corresponding with shallow trench isolation region, a source region, and a drain region; using the photoresist layer having the first opening patterned as a mask and etching the first hard mask layer to form the first opening using the dry etching process, and forming the first opening; and removing the photoresist layer having the first opening patterned. ### Claim 4 (depends on 1) The method according to claim 1, wherein after etching the first hard mask, the method further comprises: cleaning the substrate, and the first polycrystalline silicon layer and the first hard mask disposed thereon. ### Claim 5 (depends on 4) The method according to claim 4, wherein after etching the second hard mask, the method further comprises: cleaning the substrate, and the first polycrystalline silicon layer and the second hard mask disposed thereon. ### Claim 6 (depends on 5) The method according to claim 5, wherein after etching the first polycrystalline silicon layer, the method further comprises: cleaning the substrate and the second hard mask disposed thereon. ### Claim 7 (depends on 6) The method according to claim 6, wherein a SC-1 solution is used during cleaning the substrate, and the first polycrystalline silicon layer and the first hard mask disposed thereon; or during cleaning the substrate, and the first polycrystalline silicon layer and the second hard mask disposed thereon; or during cleaning the substrate and the second hard mask disposed thereon. ### Claim 8 (depends on 1) The method according to claim 1, wherein after forming the floating gate, the method further comprises: forming a laminated dielectric layer and a control gate on the floating gate, sequentially. ### Claim 9 (depends on 1) The method according to claim 1, wherein the first hard mask and the second hard mask are made of SiN. ### Claim 10 (depends on 1) The method according to claim 1, wherein the substrate is a silicon substrate. ### Claim 11 A method of manufacturing a NOR Flash device, comprising: providing a substrate having a first polycrystalline silicon layer disposed thereon; forming a first hard mask layer on the first polycrystalline silicon layer; etching the first hard mask layer to form a first opening using a dry etching process, and cleaning a gas pipeline connected to an etching cavity prior to etching the first hard mask layer; forming a second hard mask layer on the first hard mask layer, wherein the second hard mask layer covers a bottom and a side wall of the first opening; etching the second hard mask layer to form a second opening, wherein a width of the second opening is smaller than a width of the first opening; and etching the first polycrystalline silicon to form a floating gate. ### Claim 12 (depends on 11) The method according to claim 11, wherein cleaning the gas pipeline connected to the etching cavity prior to etching the first hard mask layer comprises: cleaning a pipeline containing CO gas connected to the etching cavity. ### Claim 13 (depends on 11) The method according to claim 11, wherein cleaning the gas pipeline connected to the etching cavity prior to etching the first hard mask layer comprises: cleaning a gas pipeline containing Ni connected to the etching cavity. ### Claim 14 (depends on 11) The method according to claim 11, wherein etching the first hard mask layer to form the first opening using the dry etching process comprises: spin coating a photoresist layer on the hard mask layer; exposing the photoresist layer using a mask having a first opening pattern, then developing, and forming a photoresist layer having the first opening pattern, the first opening pattern corresponding with shallow trench isolation region, a source region, and a drain region; using the photoresist layer having the first opening patterned as a mask and etching the first hard mask layer to form the first opening using the dry etching process, and forming the first opening; removing the photoresist layer having the first opening patterned. ### Claim 15 (depends on 11) The method according to claim 11, wherein after etching the first hard mask to form the first opening, the method further comprises: cleaning the substrate, and the first polycrystalline silicon layer and the first hard mask disposed thereon. ### Claim 16 (depends on 15) The method according to claim 15, wherein after etching the second hard mask to form the second opening, the method further comprises: cleaning the substrate, and the first polycrystalline silicon layer and the second hard mask disposed thereon. ### Claim 17 (depends on 16) The method according to claim 16, wherein after etching the first polycrystalline silicon layer, the method further comprises: cleaning the substrate and the second hard mask disposed thereon. ### Claim 18 (depends on 17) The method according to claim 17, wherein a SC-1 solution is used during cleaning the substrate, and the first polycrystalline silicon layer and the first hard mask disposed thereon; or during cleaning the substrate, and the first polycrystalline silicon layer and the second hard mask disposed thereon; or during cleaning the substrate and the second hard mask disposed thereon. ### Claim 19 (depends on 11) The method according to claim 11, wherein after forming the floating gate, the method further comprises: forming a laminated dielectric layer and a control gate on the floating gate, sequentially. ### Claim 20 (depends on 11) The method according to claim 11, wherein the first hard mask and the second hard mask are made of SiN.