# US 2014/0154877 A1 · Methods for fabricating integrated circuits having low resistance metal gate structures > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0154877 A1 - Document ID: US20140154877A1 - Status: Published application - Kind: A1 - Application number: 13/689,844 - Filed: 2012-11-30 - Published: 2014-06-05 - Earliest claimed: 2012-11-30 - Assignees: Globalfoundries Inc. - Applicants: Globalfoundries Inc. - Inventors: Paul R. Besser; Sean X. Lin; Valli Arunachalam - Web page: https://patentgrep.com/patent/US20140154877A1 ## CPC - H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)} - H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes} - H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)} - H10D 64/669: {the conductor further comprising additional layers of alloy material, compound material or organic material, e.g. TaN/TiAlN} - H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract Methods for fabricating integrated circuits having low resistance metal gate structures are provided. One method includes forming a metal gate stack in a FET trench formed in a FET region. The metal gate stack is etched to form a recessed metal gate stack and a recess. The recess is defined by sidewalls in the FET region and is disposed above the recessed metal gate stack. A liner is formed overlying the sidewalls and the recessed metal gate stack and defines an inner cavity in the recess. A copper layer is formed overlying the liner and at least partially fills the inner cavity. The copper layer is etched to expose an upper portion of the liner while leaving a copper portion disposed in a bottom portion of the inner cavity. Copper is electrolessly deposited on the copper portion to fill a remaining portion of the inner cavity. ## Claims ### Claim 1 A method for fabricating an integrated circuit, the method comprising: forming a metal gate stack in a FET trench formed in a FET region that comprises an interlayer dielectric material on a semiconductor substrate; etching the metal gate stack to form a recessed metal gate stack and a recess that is defined by sidewalls in the FET region and that is disposed along an upper section of the FET trench above the recessed metal gate stack; forming a liner overlying the sidewalls and the recessed metal gate stack and defining an inner cavity in the recess; forming a copper layer that overlies the liner and at least partially fills the inner cavity; etching the copper layer to expose an upper portion of the liner while leaving a copper portion disposed in a bottom portion of the inner cavity; and electrolessly depositing copper on the copper portion to fill a remaining portion of the inner cavity. ### Claim 2 (depends on 1) The method of claim 1, wherein forming the liner comprises depositing a barrier layer overlying the sidewalls and the recessed metal gate stack, and wherein the barrier layer comprises TiN and/or TaN. ### Claim 3 (depends on 2) The method of claim 2, wherein depositing the barrier layer comprises forming the barrier layer using a chemical vapor deposition process or an atomic layer deposition process. ### Claim 4 (depends on 2) The method of claim 2, wherein forming the liner comprises depositing substantially pure Ti overlying the sidewalls and the recessed metal gate stack to form a conductive layer, and wherein depositing the barrier layer comprises depositing the barrier layer overlying the conductive layer. ### Claim 5 (depends on 4) The method of claim 4, wherein depositing the substantially pure Ti comprises forming the conductive layer using a physical vapor deposition process. ### Claim 6 (depends on 2) The method of claim 2, wherein forming the liner comprises depositing a nucleation layer overlying the barrier layer, and wherein the nucleation layer comprises W and/or Ru. ### Claim 7 (depends on 6) The method of claim 6, wherein depositing the nucleation layer comprises forming the nucleation layer using a chemical vapor deposition process or an atomic layer deposition process. ### Claim 8 (depends on 1) The method of claim 1, wherein etching the copper layer comprises etching the copper layer using a wet and/or dry etching process. ### Claim 9 (depends on 1) The method of claim 1, wherein etching the copper layer comprises forming the copper portion having a thickness of from about 2 to about 20 nm. ### Claim 10 (depends on 1) The method of claim 1, further comprising: annealing copper disposed in the inner cavity to form annealed copper after electrolessly depositing copper. ### Claim 11 (depends on 10) The method of claim 10, wherein annealing copper comprises exposing copper disposed in the inner cavity to a temperature of from about 100 to about 400° C. ### Claim 12 (depends on 11) The method of claim 11, wherein annealing copper comprises exposing copper disposed in the inner cavity to the temperature for a time of from about 30 minutes to about 2 hours. ### Claim 13 (depends on 12) The method of claim 12, further comprising: removing an upper-most portion of the liner and an excess portion of the annealed copper disposed adjacent to the upper-most portion of the liner using a chemical mechanical planarization process. ### Claim 14 A method for fabricating an integrated circuit, the method comprising: forming a metal gate stack in a FET trench formed in a FET region that comprises an interlayer dielectric material on a semiconductor substrate; etching the metal gate stack to form a recessed metal gate stack and a recess that is defined by sidewalls in the FET region and that is disposed along an upper section of the FET trench above the recessed metal gate stack; forming a liner overlying the sidewalls and the recessed metal gate stack and defining an inner cavity in the recess; depositing a copper seed layer overlying the liner; reflowing the copper seed layer to form a reflowed copper seed layer that partially fills the inner cavity; etching the reflowed copper seed layer to expose an upper portion of the liner while leaving a copper portion disposed in a bottom portion of the inner cavity; and electrolessly depositing copper on the copper portion to fill a remaining portion of the inner cavity. ### Claim 15 (depends on 14) The method of claim 14, wherein reflowing the copper seed layer comprises exposing the copper seed layer to a temperature of from about 200 to about 300° C. ### Claim 16 (depends on 15) The method of claim 15, wherein reflowing the copper seed layer comprises exposing the copper seed layer to the temperature for a time of from about 30 seconds to about 15 minutes. ### Claim 17 A method for fabricating an integrated circuit, the method comprising: forming a metal gate stack in a FET trench formed in a FET region that comprises an interlayer dielectric material on a semiconductor substrate; etching the metal gate stack to form a recessed metal gate stack and a recess that is defined by sidewalls in the FET region and that is disposed along an upper section of the FET trench above the recessed metal gate stack; forming a liner overlying the sidewalls and the recessed metal gate stack and defining an inner cavity in the recess; filling the inner cavity with copper to define a copper fill; etching the copper fill to expose an upper portion of the liner while leaving a copper portion disposed in a bottom portion of the inner cavity; and electrolessly depositing copper on the copper portion to fill a remaining portion of the inner cavity. ### Claim 18 (depends on 17) The method of claim 17, wherein filling the inner cavity comprises: depositing a copper seed layer overlying the liner; reflowing the copper seed layer to form a reflowed copper seed layer that partially fills the inner cavity; and depositing copper on the reflowed copper seed layer to form the copper fill. ### Claim 19 (depends on 17) The method of claim 17, wherein filling the inner cavity comprises: depositing copper directly on the liner to form the copper fill. ### Claim 20 (depends on 17) The method of claim 17, wherein filling the inner cavity comprises: depositing copper overlying the liner using an electroplating process or a physical vapor deposition process.