# US 2014/0154876 A1 · Mechanisms for forming stressor regions in a semiconductor device

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- Number: US 2014/0154876 A1
- Document ID: US20140154876A1
- Status: Published application
- Kind: A1
- Application number: 14/173,370
- Filed: 2014-02-05
- Published: 2014-06-05
- Earliest claimed: 2011-12-13
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chun Hsiung TSAI; Tsan-Chun WANG; Su-Hao LIU; Tsz-Mei KWOK; Chii-Ming WU
- Web page: https://patentgrep.com/patent/US20140154876A1

## CPC

- H10P 32/00: Diffusion of dopants within, into or out of wafers, substrates or parts of devices (during formation of materials H10P14/00)
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 30/792: {comprising applied insulating layers, e.g. stress liners}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/125: {Shapes of junctions between the regions}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/53: the imperfections being within the semiconductor body
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/208: {of electrically inactive species}
- H10P 30/225: {of a molecular ion, e.g. decaborane}
- H10P 30/226: {at a temperature lower than room temperature}
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0133: {Manufacturing common source or drain regions between multiple IGFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method of manufacturing a semiconductor device includes performing a pre-amorphous implantation (PAI) process to form an amorphized region on a substrate. The method also includes forming a stress film over the substrate, and performing an annealing process to recrystallize the amorphized region after the stress film is formed. The method further includes forming a recess region on the substrate. The recess region overlies the recrystallized region. The method additionally includes forming an epitaxial stress-inducing material in the recess region.

## Claims

### Claim 1

A method of manufacturing a semiconductor device, the method comprising:
performing a pre-amorphous implantation (PAI) process to form an amorphized region on a substrate;
forming a stress film over the substrate;
performing an annealing process to recrystallize the amorphized region after the stress film is formed;
forming a recess region on the substrate, wherein the recess region overlies the recrystallized region; and
forming an epitaxial stress-inducing material in the recess region.

### Claim 2 (depends on 1)

The method of claim 1, wherein the recrystallized region includes at least one dislocation.

### Claim 3 (depends on 1)

The method of claim 1, wherein performing the PAI process includes implanting the substrate with silicon (Si) or germanium (Ge) implant species.

### Claim 4 (depends on 1)

The method of claim 1, wherein the annealing process includes a rapid thermal annealing (RTA) process, a millisecond thermal annealing (MSA) process, or a microsecond thermal annealing (OA) process.

### Claim 5 (depends on 1)

The method of claim 1, wherein the epitaxial stress-inducing material includes SiC, SiP, or SiCP.

### Claim 6 (depends on 1)

The method of claim 1, wherein forming the recess region utilizes a wet etch after a dry etch.

### Claim 7 (depends on 1)

The method of claim 1, further comprising:
forming spacers on each side of a gate stack, wherein the gate stack is on the substrate.

### Claim 8 (depends on 1)

The method of claim 1, wherein performing the PAI processes comprises forming the amorphized region having a depth ranging from about 10 nm to about 150 nm.

### Claim 9 (depends on 1)

The method of claim 1, wherein performing the PAI process comprises implanting a species in the substrate, wherein the species comprises at least one of silicon, germanium, argon, xenon, or boron difluoride.

### Claim 10 (depends on 1)

The method of claim 1, wherein performing the PAI process comprises implanting a species in the substrate at a temperature ranging from about −100° C. to about 25° C.

### Claim 11 (depends on 1)

The method of claim 1, wherein performing the PAI process comprises implanting a species in the substrate in a concentration ranging from about 1×1014 atoms/cm2 to about 2×1015 atoms/cm2.

### Claim 12 (depends on 1)

The method of claim 1, wherein forming the stress film comprises forming the stress film to retard a growth rate in the direction of the amorphized region.

### Claim 13 (depends on 1)

The method of claim 1, wherein forming the recess region comprises forming the recess region having a depth ranging from about 100 angstroms (Å) and about 800 Å and a width at a surface of the substrate ranging from about 20 nm to about 200 nm.

### Claim 14

A method of manufacturing a semiconductor device, the method comprising:
performing a pre-amorphous implantation (PAI) process to form an amorphized region on a substrate;
forming a stress film over the substrate;
forming at least one dislocation in the amorphized region, wherein a pinch off point of the at least one dislocation is spaced from a bottom edge of the amorphized region by a distance ranging from about 10 nanometers (nm) to about 40 nm;
forming a recess region on the substrate, wherein the recess region overlies at least a portion of the at least on dislocation; and
forming an epitaxial stress-inducing material in the recess region.

### Claim 15 (depends on 14)

The method of claim 14, wherein forming the at least one dislocation comprises performing a rapid thermal anneal process, a millisecond thermal anneal process, or a microsecond thermal anneal process.

### Claim 16 (depends on 14)

The method of claim 14, wherein forming the at least on dislocation comprises:
performing a pre-heating process; and
performing a main heating process after the pre-heating process.

### Claim 17 (depends on 16)

The method of claim 16, wherein performing the pre-heating process comprises heating the substrate at a first temperature ranging from about 200° C. to about 700° C. for a first duration ranging from about 10 seconds to about 10 minutes, and performing the main heating process comprises heating the substrate at a second temperature ranging from about 800° C. to about 1400° C. for a second duration ranging from about 1 millisecond to about 5 hours.

### Claim 18 (depends on 14)

The method of claim 14, wherein forming the recess region comprises performing a dry etching process using an etchant comprising at least one of NF3, Cl2, SF4, He, Ar, or CF4.

### Claim 19 (depends on 14)

The method of claim 14, wherein forming the recess region comprises performing a wet etching process using an etchant comprising at least one of NH4OH, HF, or TMAH.

### Claim 20

A method of making a semiconductor device, the method comprising:
forming a first stress region in a semiconductor substrate, the first stress region including at least one dislocation, wherein a gate structure is disposed over a channel region of the semiconductor substrate; and
forming a second stress region in the semiconductor substrate and overlying the first stress region.