# US 2014/0154865 A1 · Shallow trench isolation structures

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- Number: US 2014/0154865 A1
- Document ID: US20140154865A1
- Status: Published application
- Kind: A1
- Application number: 14/173,296
- Filed: 2014-02-05
- Published: 2014-06-05
- Earliest claimed: 2012-06-25
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Bruce B. Doris; Kangguo Cheng; Balasubramanian S. Haran; Ali Khakifirooz; Pranita Kerber; Arvind Kumar; Shom Ponoth
- Web page: https://patentgrep.com/patent/US20140154865A1

## CPC

- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10P 90/1906: {Preparing SOI wafers}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/061: {using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Shallow trench isolation structures are provided for use with UTBB (ultra-thin body and buried oxide) semiconductor substrates, which prevent defect mechanisms from occurring, such as the formation of electrical shorts between exposed portions of silicon layers on the sidewalls of shallow trench of a UTBB substrate, in instances when trench fill material of the shallow trench is subsequently etched away and recessed below an upper surface of the UTBB substrate.

## Claims

### Claim 1

A method of forming a semiconductor device, comprising:
forming a high-k gate dielectric layer on a semiconductor substrate comprising a first silicon layer, a second silicon layer, and a buried oxide layer disposed between the first silicon layer and the second silicon layer; and
forming a shallow trench isolation structure formed in the semiconductor substrate, wherein forming a shallow trench isolation structure comprises:
forming a shallow trench in the substrate through the first silicon layer, the buried oxide layer and partially through the second silicon layer;
forming a first liner conformally lining the shallow trench; and
filling the shallow trench with a trench fill material,
wherein the first liner is formed of a material having etch selectivity with regard to the trench fill material, and wherein the first liner is formed to serve as a protective liner to prevent electrical shorts from forming between the first and second silicon layer in the shallow trench.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first liner is a high-k dielectric liner.

### Claim 3 (depends on 1)

The method of claim 1, wherein forming the shallow trench isolation structure further comprises forming a second liner directly on exposed surfaces of the first and second silicon layers in the shallow trench, prior to forming the first liner.

### Claim 4 (depends on 3)

The method of claim 3, wherein the second liner is formed of oxynitride.

### Claim 5 (depends on 1)

The method of claim 1, wherein a thickness of the buried oxide layer is in a range of about 5 nm to about 75 nm.

### Claim 6 (depends on 1)

The method of claim 1, wherein the trench fill material comprises an oxide material.