# US 2014/0154859 A1 · Methods and Vehicles for High Productivity Combinatorial Testing of Materials for Resistive Random Access Memory Cells > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0154859 A1 - Document ID: US20140154859A1 - Status: Published application - Kind: A1 - Application number: 13/705,516 - Filed: 2012-12-05 - Published: 2014-06-05 - Earliest claimed: 2012-12-05 - Assignees: Intermolecular, Inc. - Applicants: Intermolecular Inc. - Inventors: Vidyut Gopal; Tony P. Chiang; Imran Hashim; Randall J. Higuchi; Robert A. Huertas; Hieu Pham; Yun Wang - Web page: https://patentgrep.com/patent/US20140154859A1 ## CPC - H10P 74/277: {Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers} - H10N 70/24: {based on migration or redistribution of ionic species, e.g. anions, vacancies} - H10N 70/883: {Oxides or nitrides} - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR ## Abstract Provided are methods for processing different materials on the same substrate for high throughput screening of multiple ReRAM materials. A substrate may be divided into multiple site isolated regions, each region including one or more base structures operable as bottom electrodes of ReRAM cells. Different test samples may be formed over these base structures in a combinatorial manner. Specifically, each site isolated region may receive a test sample that has a different characteristic than at least one other sample provided in another region. The test samples may have different compositions and/or thicknesses or be deposited using different techniques. These different samples are then etched in the same operation to form portions of the samples. Each portion is substantially larger than the corresponding base structure and fully covers this base structure to protect the interface between the base structure and the portion during etching. ## Claims ### Claim 1 A method comprising: providing a substrate comprising a plurality of site isolated regions, each site isolated region comprises at least one base structure comprising a conductive material, wherein each base structure is connected to a separate connector structure for connecting to an electrical lead of a test probe; forming test samples over the base structures in each of the site isolated regions, the test samples formed in a combinatorial manner such that each site isolated region receives one test sample having a different characteristic than at least one test sample of another site isolated region, the test samples comprising dielectric materials, each test sample forming an interface layer with one of the base structures; and etching the test samples in the same operation while each test sample protects the interface formed with the one of the base structures during etching, wherein etching forms test sample portions from the test samples, each test sample portion fully covering a base structure provided under this test sample portion. ### Claim 2 (depends on 1) The method of claim 1, wherein each test sample portion has a dimension, in a plane of the substrate, that is at least four times greater than a corresponding dimension of the base structure provided under this test sample portion. ### Claim 3 (depends on 1) The method of claim 1, wherein each test sample portion is concentric to the base structure provided under the test sample portion. ### Claim 4 (depends on 1) The method of claim 1, wherein each test sample portion has a dimension, in a plane of the substrate, that is at least 1 micrometer. ### Claim 5 (depends on 4) The method of claim 4, wherein each base structure has a dimension, in a plane of the substrate, that is less than 600 nanometers. ### Claim 6 (depends on 1) The method of claim 1, wherein edges of each test sample portion and edges of the base structure provided under this test sample portion are separated by at least about 20 micrometers. ### Claim 7 (depends on 1) The method of claim 1, wherein the base structures of the plurality of site isolated regions are formed from the same layer. ### Claim 8 (depends on 1) The method of claim 1, wherein at least one base structure of one site isolated region has a different composition than at least one base structure of another site isolated region. ### Claim 9 (depends on 1) The method of claim 1, wherein the substrate is cleaved into a plurality of dies prior to etching the test samples. ### Claim 10 (depends on 1) The method of claim 1, further comprising forming one or more layers over the test samples, wherein the one or more layers and the test samples are etched in the same operation, and wherein each layer portion formed during etching coincides with a test sample portion provided under this layer portion. ### Claim 11 (depends on 10) The method of claim 10, wherein each layer portion formed during etching forms a contact surface for making an electrical connection with a probe. ### Claim 12 (depends on 10) The method of claim 10, wherein the base structures are operable as first electrodes of resistive switching memory cells. ### Claim 13 (depends on 12) The method of claim 12, wherein the test sample portions are operable as resistive switching layers of the resistive switching memory cell. ### Claim 14 (depends on 13) The method of claim 13, wherein the layer portions are operable as second electrodes of the resistive switching memory cells. ### Claim 15 (depends on 1) The method of claim 1, wherein the substrate comprises connector structures and wherein each base structure is electrically connected to a separate connector structure. ### Claim 16 (depends on 15) The method of claim 15, wherein one or more of the connector structures are covered with one of the test samples prior to etching and are not covered by that test sample after etching. ### Claim 17 (depends on 1) The method of claim 1, wherein the test samples are formed using one of a High Productivity Combinatorial Atomic Layer Deposition (HPC-ALD) technique or a High Productivity Combinatorial Physical Vapor Deposition (HPC-PVD) technique. ### Claim 18 (depends on 1) The method of claim 1, wherein etching the test samples is performed using the same process conditions. ### Claim 19 A method comprising: providing a substrate comprising a first site isolated region and a second site isolated region, the first site isolated region comprising a first base structure, the second site isolated region comprising a second base structure, wherein the first base structure and the second base structure have the same composition and thickness, wherein the first base structure and the second base structure are formed from a conductive material; wherein the first base structure is connected to a first connector structure for connecting to an electrical lead of a test probe; wherein the second base structure is connected to a second connector structure for connecting to an electrical lead of a test probe; forming a first test sample over the first base structure and forming a second test sample over the second base structure, the first test sample and the second test sample have different compositions, the first test sample and the second test sample formed from different dielectric materials, wherein the first base structure and the first test sample form a first interface and wherein the second base structure and the second test sample form a second interface, forming a layer over the first test sample and the second test sample; and etching the first test sample, the second test sample, and the layer in the same operation while the first test sample protects the first interface and the second test sample protects the second interface during etching, wherein etching forms a first stack comprising a portion of the first test sample and a first portion of the layer, wherein etching also forms a second stack comprising a portion of the second test sample and a second portion of the layer, wherein the first stack fully covers the first base structure forming a first resistive random access memory cell and the second stack fully covers the second base structure forming a second resistive random access memory cell. ### Claim 20 (depends on 19) The method of claim 19, wherein etching the first test sample, the second test sample, and the layer is performed using the same process conditions.