# US 2014/0154857 A1 · Memory Device And Method For Making Same

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- Number: US 2014/0154857 A1
- Document ID: US20140154857A1
- Status: Published application
- Kind: A1
- Application number: 13/924,635
- Filed: 2013-06-24
- Published: 2014-06-05
- Earliest claimed: 2008-07-09
- Assignees: Infineon Technologies AG
- Inventors: Armin TILKE
- Web page: https://patentgrep.com/patent/US20140154857A1

## CPC

- H10D 10/021: {of heterojunction BJTs [HBT]}
- H10B 63/32: {of the bipolar type}
- H10B 63/80: {Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays}
- H10B 69/00: Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
- H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect}
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10N 70/8828: {Tellurides, e.g. GeSbTe}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

Embodiments relate to a method of forming a memory array,comprising: forming a collector layer; forming a plurality of collector regions in the collector layer; forming a plurality of base regions over the collector region; forming a plurality of emitter regions over the base regions; forming a plurality of memory elements over the emitter regions, wherein the collector regions, base regions and emitter regions form heterojunction bipolar transistors.

## Claims

### Claim 1

A method of forming a memory array,comprising:
forming a collector layer;
forming a plurality of collector regions in said collector layer;
forming a plurality of base regions over said collector region;
forming a plurality of emitter regions over said base regions;
forming a plurality of memory elements over said emitter regions,
wherein said collector regions, base regions and emitter regions form heterojunction bipolar transistors.

### Claim 2 (depends on 1)

The method of claim 1, wherein forming said collector regions includes forming insulating trenches in said collector layers, said collector regions being spaced apart from each other by said insulating trenches.

### Claim 3 (depends on 1)

The method of claim 1, wherein said forming said base regions includes forming a base layer over said collector regions and over said insulating trenches using a differential epitaxial deposition.

### Claim 4 (depends on 3)

The method of claim 3, wherein said differential epitaxial deposition forms monocrystalline regions over said collector regions and polycrystalline regions over said insulating trenches, said monocrystalline regions corresponding to said base regions.

### Claim 5 (depends on 4)

The method of claim 4, further comprising, after forming said polycrystalline regions, doping said polycrystalline regions.

### Claim 6 (depends on 5)

The method of claim 5, wherein said polycrystalline regions are doped by outdiffusion from said insulating trenches.

### Claim 7 (depends on 5)

The method of claim 5, wherein polycrystalline trenches are doped with boron.

### Claim 8 (depends on 1)

The method of claim 1, further including forming insulting trenches in said base layer after forming said base regions.

### Claim 9 (depends on 1)

The method of claim 1, wherein said collector regions comprise n-type material, said base regions comprise p-type material and said emitter regions comprise n-type material.