# US 2014/0154854 A1 · Methods for fabricating integrated circuits

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- Number: US 2014/0154854 A1
- Document ID: US20140154854A1
- Status: Published application
- Kind: A1
- Application number: 14/027,837
- Filed: 2013-09-16
- Published: 2014-06-05
- Earliest claimed: 2011-09-13
- Assignees: Globalfopundries, Inc.
- Applicants: Globalfoundries, Inc.
- Inventors: Andy Wei; Peter Baars; Erik P. Geiss
- Web page: https://patentgrep.com/patent/US20140154854A1

## CPC

- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/259: {Source or drain electrodes being self-aligned with the gate electrode and having bottom surfaces higher than the interface between the channel and the gate dielectric}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Methods are provided for fabricating integrated circuits. One method includes etching a plurality of trenches into a silicon substrate and filling the trenches with an insulating material to delineate a plurality of spaced apart silicon fins. A layer of undoped silicon is epitaxially grown to form an upper, undoped region of the fins. Dummy gate structures are formed overlying and transverse to the plurality of fins and a back fill material fills between the dummy gate structures. The dummy gate structures are removed to expose a portion of the fins and a high-k dielectric material and a work function determining gate electrode material are deposited overlying the portion of the fins. The back fill material is removed to expose a second portion and metal silicide contacts are formed on the second portion. Conductive contacts are then formed to the work function determining material and to the metal silicide.

## Claims

### Claim 1

A method for fabricating an integrated circuit comprising:
in a bulk silicon substrate, forming a first device area and a second device area, the first device area separated from the second device area by shallow trench isolation;
dividing the first device area into a plurality of spaced apart silicon fins separated by a shallow trench isolation insulator;
epitaxially growing a layer of undoped channel silicon overlying portions of the first device area and the second device area;
forming a first dummy gate overlying and transverse to the fins and a second dummy gate overlying the second device area;
forming dummy contacts spaced apart from and adjacent the first dummy gate and the second dummy gate;
removing the first dummy gate and the second dummy gate;
etching the shallow trench isolation insulator to expose a portion of the fins;
depositing a layer of gate dielectric material and a layer of work function determining material overlying the undoped channel silicon;
removing the dummy contacts to expose portions of the fins and of the second device area;
forming a metal silicide contacting the exposed portions; and
forming an electrical contact to the layer of work function material and the metal silicide.

### Claim 2 (depends on 1)

The method of claim 1 further comprising:
doping the first device area and the second device area with conductivity determining dopants of a first conductivity type; and
implanting ions of second conductivity determining type into the spaced apart fins and into the second device area using the first dummy gate and the second dummy gate as ion implantation masks to form source and drain regions aligned with the first dummy gate and the second dummy gate.

### Claim 3 (depends on 1)

The method of claim 1 wherein epitaxially growing a layer of undoped channel silicon comprises:
epitaxially growing a first layer of silicon admixed with carbon overlying the plurality of spaced apart silicon fins and the second device area; and
epitaxially growing a second layer of undoped silicon overlying the first layer.

### Claim 4 (depends on 1)

The method of claim 1 wherein epitaxially growing a layer of undoped channel silicon comprises:
removing the first dummy gate to expose a portion of the fins and removing the second dummy gate to expose a portion of the second device area;
etching a first trench into the exposed portion of the fins and a second trench into the exposed portion of the second device area; and
epitaxially growing a first layer of undoped silicon to fill the first trench and a second layer of undoped silicon to fill the second trench.

### Claim 5 (depends on 1)

The method of claim 1 wherein removing the dummy contacts comprises:
depositing a layer of spin on glass overlying the undoped channel silicon; and
etching the dummy contacts using the spin on glass as an etch mask.

### Claim 6 (depends on 1)

The method of claim 1 wherein forming a first dummy gate and a second dummy gate comprises depositing and patterning a layer of silicon germanium.

### Claim 7

A method for fabricating an integrated circuit comprising:
providing a semiconductor substrate having a first device area and a second device area;
forming fins in the first device area;
epitaxially growing a layer of undoped channel silicon overlying portions of the first device area and the second device area;
forming first dummy gates overlying the fins and second dummy gates overlying the second device area and defining channels;
forming sidewall spacers on the dummy gate structures;
depositing spin on glass material between the dummy gate structures;
removing the dummy gate structures using the spin on glass material as an etch mask;
depositing a layer of high-k gate insulator and a capping layer overlying the channels;
removing the spin on glass to expose source and drain regions adjacent to and spaced apart from the channels;
forming metal silicide contacts to the source and drain regions;
depositing work function determining material overlying the high-k gate insulator; and
depositing metal contacting the metal silicide contacts and the work function determining material.

### Claim 8 (depends on 7)

The method of claim 7 further comprising, after forming sidewall spacers, growing by a process of selective epitaxial growth, a layer of silicon admixed with an element selected from the group consisting of germanium and carbon, to form raised source and drain structures.

### Claim 9 (depends on 7)

The method of claim 7 wherein forming metal silicide contacts comprises forming nickel silicide contacts and wherein depositing work function determining material comprises depositing a material selected from the group consisting of titanium nitride and titanium aluminum nitride.

### Claim 10 (depends on 7)

The method of claim 7 wherein depositing metal comprises depositing the same metal contacting both the metal silicide contacts and the work function determining material.

### Claim 11 (depends on 7)

The method of claim 7 further comprising growing a layer of undoped silicon overlying the silicon substrate.

### Claim 12 (depends on 7)

The method of claim 7 further comprising:
doping the first device area and the second device area with conductivity determining dopants of a first conductivity type; and
implanting ions of second conductivity determining type into the spaced apart fins and into the second device area using the first dummy gates and the second dummy gates as ion implantation masks to form source and drain regions aligned with the first dummy gates and the second dummy gates.

### Claim 13 (depends on 7)

The method of claim 7 wherein epitaxially growing a layer of undoped channel silicon comprises:
epitaxially growing a first layer of silicon admixed with carbon overlying the plurality of spaced apart silicon fins and the second device area; and
epitaxially growing a second layer of undoped silicon overlying the first layer.

### Claim 14 (depends on 7)

The method of claim 7 wherein epitaxially growing a layer of undoped channel silicon comprises:
removing the first dummy gates to expose a portion of the fins and removing the second dummy gates to expose a portion of the second device area;
etching a first trench into the exposed portion of the fins and a second trench into the exposed portion of the second device area; and
epitaxially growing a first layer of undoped silicon to fill the first trench and a second layer of undoped silicon to fill the second trench.

### Claim 15 (depends on 7)

The method of claim 7 wherein epitaxially growing a layer of undoped channel silicon comprises:
removing the first dummy gates to expose first portions of the fins;
etching the first portions of the fins to form recesses; and
epitaxially growing a first layer of undoped silicon to fill the recesses.

### Claim 16

A method for fabricating a silicon integrated circuit comprising:
forming shallow trench isolation to define an area of a silicon substrate;
forming dummy gate structures overlying the area and defining a channel in the area;
forming sidewall spacers on the dummy gate structures;
depositing spin on glass material between the dummy gate structures;
removing the dummy gate structures using the spin on glass material as an etch mask;
depositing a layer of high-k gate insulator and a capping layer overlying the channel;
removing the spin on glass to expose source and drain regions adjacent to and spaced apart from the channel;
forming metal silicide contacts to the source and drain regions;
depositing work function determining material overlying the high-k gate insulator; and
depositing metal contacting the metal silicide contacts and the work function determining material.

### Claim 17 (depends on 16)

The method of claim 16 further comprising, after forming sidewall spacers, growing by a process of selective epitaxial growth, a layer of silicon admixed with an element selected from the group consisting of germanium and carbon, to form raised source and drain structures.

### Claim 18 (depends on 16)

The method of claim 16 wherein forming metal silicide contacts comprises forming nickel silicide contacts and wherein depositing work function determining material comprises depositing a material selected from the group consisting of titanium nitride and titanium aluminum nitride.

### Claim 19 (depends on 16)

The method of claim 16 wherein depositing metal comprises depositing the same metal contacting both the metal silicide contacts and the work function determining material.

### Claim 20 (depends on 16)

The method of claim 16 further comprising growing a layer of undoped silicon overlying the silicon substrate.