# US 2014/0154853 A1 · Method for manufacturing n-type mosfet

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- Number: US 2014/0154853 A1
- Document ID: US20140154853A1
- Status: Published application
- Kind: A1
- Application number: 13/878,046
- Filed: 2012-12-07
- Published: 2014-06-05
- Earliest claimed: 2012-11-30
- Assignees: Institute of Microelectronics, Chinese Academy of Sciences
- Inventors: Qiuxia Xu; Huilong Zhu; Huajie Zhou; Gaobo Xu
- Web page: https://patentgrep.com/patent/US20140154853A1

## CPC

- H10D 64/01338: {with a treatment, e.g. annealing, after the formation of the conductor}
- H10D 64/01318: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314)}
- H10D 64/685: {being perpendicular to the channel plane}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 64/693: {the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 64/669: {the conductor further comprising additional layers of alloy material, compound material or organic material, e.g. TaN/TiAlN}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

The present disclosure discloses a method for manufacturing an N-type MOSFET, comprising: forming a part of the MOSFET on a semiconductor substrate, the part of the MOSFET comprising source/drain regions in the semiconductor substrate, a replacement gate stack between the source/drain regions above the semiconductor substrate, and a gate spacer surrounding the replacement gate stack; removing the replacement gate stack of the MOSFET to form a gate opening exposing a surface of the semiconductor substrate; forming an interface oxide layer on the exposed surface of the semiconductor; forming a high-K gate dielectric layer on the interface oxide layer in the gate opening; forming a first metal gate layer on the high-K gate dielectric layer; implanting dopant ions into the first metal gate layer; and performing annealing to cause the dopant ions to diffuse and accumulate at an upper interface between the high-K gate dielectric layer and the first metal gate layer and a lower interface between the high-K gate dielectric layer and the interface oxide layer, and also to generate electric dipoles by interfacial reaction at the lower interface between the high-K gate dielectric layer and the interface oxide layer.

## Claims

### Claim 1

A method for manufacturing an N-type MOSFET, comprising:
forming a part of the MOSFET on a semiconductor substrate, the part of the MOSFET comprising source/drain regions in the semiconductor substrate, a replacement gate stack between the source/drain regions above the semiconductor substrate, and a gate spacer surrounding the replacement gate stack;
removing the replacement gate stack of the MOSFET to form a gate opening exposing a surface of the semiconductor substrate;
forming an interface oxide layer on the exposed surface of the semiconductor;
forming a high-K gate dielectric layer on the interface oxide layer in the gate opening;
forming a first metal gate layer on the high-K gate dielectric layer;
implanting dopant ions into the first metal gate layer;
forming a second metal gate layer on the first metal gate layer to fill the gate opening; and
performing annealing to cause the dopant ions to diffuse and accumulate at an upper interface between the high-K gate dielectric layer and the first metal gate layer and a lower interface between the high-K gate dielectric layer and the interface oxide layer, and also to generate electric dipoles by interfacial reaction at the lower interface between the high-K gate dielectric layer and the interface oxide layer.

### Claim 2 (depends on 1)

The method according to claim 1, wherein the high-K gate dielectric layer comprise any one selected from ZrO2, ZrON, ZrSiON, HfZrO, HfZrON, HfON, HfO2, HfAlO, HfAlON, HfSiO, HfSiON, HfLaO, HfLaON, and any combination thereof.

### Claim 3 (depends on 1)

The method according to claim 1, wherein the high-K gate dielectric layer has a thickness of about 1.5-5 nm.

### Claim 4 (depends on 1)

The method according to claim 1, wherein the high-K gate dielectric layer is formed by any one of atom layer deposition, physical vapor deposition, and metal organic chemical vapor deposition.

### Claim 5 (depends on 4)

The method according to claim 4, further comprising performing additional annealing after forming the high-K gate dielectric layer to improve quality of the high-K gate dielectric layer.

### Claim 6 (depends on 1)

The method according to claim 1, wherein the first metal gate layer comprises any one selected from TiN, TaN, MoN, WN, TaC, TaCN, and any combination thereof.

### Claim 7 (depends on 1)

The method according to claim 1, wherein the first metal gate layer has a thickness of about 2-10 nm.

### Claim 8 (depends on 1)

The method according to claim 1, wherein the second metal gate layer comprises any one selected from W, Ti, TiAl, Al, Mo, Ta, TiN, TaN, WN, and any combination thereof.

### Claim 9 (depends on 1)

The method according to claim 1, wherein in implanting the dopant ions into the first metal gate layer, energy and dosage of ion implantation is controlled according to a desired threshold voltage to cause the dopant ions to distribute only in the first metal gate layer.

### Claim 10 (depends on 9)

The method according to claim 9, wherein the energy of the ion implantation is about 0.2 KeV-30 KeV.

### Claim 11 (depends on 9)

The method according to claim 9, wherein the dosage of the ion implantation is about 1E13-1E15 cm−2.

### Claim 12 (depends on 1)

The method according to claim 1, wherein dopant ions implanted into the first metal gate layer is capable of reducing effective work function.

### Claim 13 (depends on 12)

The method according to claim 12, wherein the dopant is any one selected from P, As, Sb, La, Er, Dy, Gd, Sc, Yb, Er, and Tb.

### Claim 14 (depends on 1)

The method according to claim 1, wherein the annealing is performed in inert gas environment or weak reduction gas environment at about 350° C.-450° C. for about 20-90 minutes.