# US 2014/0154843 A1 · Method for Top-side Cooled Semiconductor Package with Stacked Interconnection Plates

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- Number: US 2014/0154843 A1
- Document ID: US20140154843A1
- Status: Published application
- Kind: A1
- Application number: 14/173,151
- Filed: 2014-02-05
- Published: 2014-06-05
- Earliest claimed: 2008-12-01
- Assignees: Alpha and Omega Semiconductor Incorprated
- Applicants: Alpha and Omega Semiconductor Incorprated
- Inventors: Kai Liu; François Hébert; Lei Shi
- Web page: https://patentgrep.com/patent/US20140154843A1

## CPC

- H10W 74/01: Manufacture or treatment
- H10W 70/461: {specially adapted for cooling}
- H10W 70/466: {Tape carriers or flat leads}
- H10W 70/481: {for devices being provided for in groups H10D8/00 - H10D48/00}
- H10W 72/60: Strap connectors, e.g. thick copper clips for grounding of power devices
- H10W 95/00: Packaging processes not covered by the other groups of this subclass
- H10W 72/07336: {Soldering or alloying}
- H10W 72/076: {of strap connectors}
- H10W 72/07636: {Soldering or alloying}
- H10W 72/07637: {using a polymer adhesive, e.g. an adhesive based on silicone or epoxy}
- H10W 72/07652: {changes in structures or sizes}
- H10W 72/07653: {changes in shapes}
- H10W 72/352: {comprising metals or metalloids, e.g. solders}
- H10W 72/627: {Multiple strap connectors having different structures or shapes}
- H10W 72/631: {Shapes of strap connectors}
- H10W 72/886: {Die-attach connectors and strap connectors}
- H10W 72/931: {Shapes of bond pads}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/766: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A top-side cooled semiconductor package with stacked interconnection plate is disclosed. The semiconductor package includes a circuit substrate with terminal leads, a semiconductor die atop the circuit substrate, a low thermal resistance intimate interconnection plate for bonding and interconnecting a top contact area of the semiconductor die with the circuit substrate, a low thermal resistance stacked interconnection plate atop the intimate interconnection plate for top-side cooling, a molding encapsulant for encapsulating the package except for exposing a top surface of the stacked interconnection plate to maintain effective top-side cooling. The top portion of the stacked interconnection plate can include a peripheral overhang above the intimate interconnection plate. The peripheral overhang allows for a maximized exposed top surface area for heat dissipation independent of otherwise areal constraints applicable to the intimate interconnection plate. The stacked interconnection plate can be partially etched or three dimensionally formed to create the peripheral overhang.

## Claims

### Claim 1

A method of packaging a top-side cooled semiconductor package of a semiconductor die interconnected with a plurality of elevation-adaptive intimate interconnection plates and elevation-adaptive stacked interconnection plates, the method comprises:
a) providing a circuit substrate having a plurality of terminal leads for external electrical connection;
b) providing the semiconductor die and attaching it atop the circuit substrate;
c) providing and attaching one or more intimate interconnection plates to top contact areas of said semiconductor die and said circuit substrate for electrical connection between said top contact areas and said terminal leads; and
d) providing and attaching a number of stacked interconnection plates atop a selected intimate interconnection plate; and
e1) placing a detachable mask over a top surface of the number of stacked interconnection plates to be ultimately exposed;
e2) molding an encapsulant over the circuit substrate, the semiconductor die, the one or more intimate interconnection plates and the number of stacked interconnection plates;
e3) removing the detachable mask to expose the top surface of the number of stacked interconnection plates to maintain effective top-side cooling.

### Claim 2 (depends on 1)

The method of claim 1 wherein said circuit substrate is a leadframe and providing the circuit substrate further comprises dispensing a bonding agent atop the leadframe die pads and leadframe leads.

### Claim 3 (depends on 1)

The method of claim 1 wherein providing and attaching the number of stacked interconnection plates further comprising:
d1) dispensing a bonding agent atop a selected number of the intimate interconnection plates for connecting the number of stacked interconnection plates with the intimate interconnection plates; and
d2) treating the package in progress to activate the bonding agent thus forming a permanent bond between the number of stacked interconnection plates and the selected intimate interconnection plates.