# US 2014/0154842 A1 · Carrier, semiconductor package and fabrication method thereof

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- Number: US 2014/0154842 A1
- Document ID: US20140154842A1
- Status: Published application
- Kind: A1
- Application number: 14/174,988
- Filed: 2014-02-07
- Published: 2014-06-05
- Earliest claimed: 2012-01-20
- Assignees: Siliconware Precision Industries Co., Ltd.
- Applicants: Siliconware Precision Industries Co., Ltd.
- Inventors: Chiang-Cheng Chang; Meng-Tsung Lee; Jung-Pang Huang; Shih-Kuang Chiu
- Web page: https://patentgrep.com/patent/US20140154842A1

## CPC

- H10W 74/01: Manufacture or treatment
- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10P 72/10: using carriers specially adapted therefor, e.g. front opening unified pods [FOUP]
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 74/014: {using batch processing}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/129: {forming a chip-scale package [CSP]}
- H10P 72/16: {Trays for chips}
- H10P 72/34: {the wafers being stored in a carrier, involving loading and unloading}
- H10P 72/50: for positioning, orientation or alignment
- H10P 72/70: for supporting or gripping
- H10W 70/042: {Etching}
- H10W 70/655: Fan-out layouts
- H10W 72/0198: {batch processes}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/922: {Bond pads being integral with underlying chip-level interconnections}
- H10W 72/9413: {on encapsulations}
- H10W 74/017: {Auxiliary layers for moulds, e.g. release layers or layers preventing residue}
- H10W 74/10: characterised by their shape or disposition
- H10W 74/111: {the semiconductor body being completely enclosed}
- H10W 74/114: {by a substrate and the encapsulations}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A fabrication method of a semiconductor package includes the steps of: providing a carrier having a concave portion and a releasing layer formed on a surface thereof; disposing a chip on the releasing layer in the concave portion; forming an encapsulant on the chip and the releasing layer; removing the releasing layer and the carrier; and forming a circuit structure on the encapsulant and the chip. The design of the concave portion facilitates alignment of the chip to prevent it from displacement, thereby improving the product reliability. A semiconductor package fabricated by the fabrication method is also provided.

## Claims

### Claim at position 1

1-3. (canceled)

### Claim 4

A fabrication method of a semiconductor package, comprising the steps of:
providing a carrier having a concave portion and a releasing layer formed on a surface thereof;
disposing a chip on the releasing layer in the concave portion, wherein the chip has an active surface with a plurality of electrode pads and an inactive surface opposite to the active surface, the chip being disposed on the releasing layer via the active surface thereof;
forming an encapsulant on the chip and the releasing layer;
removing the releasing layer and the carrier so as to expose the active surface of the chip; and
forming a circuit structure on the encapsulant and the active surface of the chip, wherein the circuit structure is electrically connected to the electrode pads of the chip.

### Claim 5 (depends on 4)

The method of claim 4, wherein the carrier is made of glass or metal.

### Claim 6 (depends on 4)

The method of claim 4, wherein a plurality of concave portions are provided and array arranged on the carrier.

### Claim 7 (depends on 6)

The method of claim 6, after forming the circuit structure on the encapsulant and the active surface of the chip, further comprising performing a singulation process.

### Claim 8 (depends on 4)

The method of claim 4, wherein the releasing layer is made of a hydrophobic material, an inorganic material or a polymer material.

### Claim 9 (depends on 4)

The method of claim 4, wherein the carrier is removed first and then the releasing layer is removed.

### Claim 10 (depends on 4)

The method of claim 4, wherein the releasing layer and the carrier are removed simultaneously.

### Claim 11 (depends on 4)

The method of claim 4, wherein the circuit structure has at least a dielectric layer formed on the encapsulant and the active surface of the chip, a circuit layer formed on the dielectric layer and a plurality of conductive vias formed in the dielectric layer for electrically connecting the circuit layer and the electrode pads of the chip.

### Claim 12 (depends on 11)

The method of claim 11, further comprising forming an insulating protection layer on the outermost dielectric layer of the circuit structure and forming a plurality of openings in the insulating protection layer such that portions of the circuit layer are exposed through the openings so as for conductive elements to be disposed thereon.

### Claim 13

A carrier for fabricating a semiconductor package, having a concave portion and a releasing layer disposed on a surface thereof.

### Claim 14 (depends on 13)

The carrier of claim 13, wherein the carrier is made of glass or metal,

### Claim 15 (depends on 13)

The carrier of claim 13, wherein the releasing layer is made of a hydrophobic material, an inorganic material or a polymer material.