# US 2014/0154841 A1 · Hermetic Wafer Level Packaging > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0154841 A1 - Document ID: US20140154841A1 - Status: Published application - Kind: A1 - Application number: 14/174,214 - Filed: 2014-02-06 - Published: 2014-06-05 - Earliest claimed: 2010-07-29 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Richard Chu; Martin Liu; Chia-Hua Chu; Yuan-Chih Hsieh; Chung-Hsien Lin; Lan-Lin Chao; Chun-Wen Cheng; Mingo Liu - Web page: https://patentgrep.com/patent/US20140154841A1 ## CPC - H10W 72/0198: {batch processes} - B81C 1/00269: {Bonding of solid lids or wafers to the substrate} - H10W 90/00: Package configurations - B81B 2207/015: the micromechanical device and the control or processing electronics being integrated on the same substrate - B81C 2203/0109: Bonding an individual cap on the substrate - B81C 2203/0771: Stacking the electronic processing unit and the micromechanical structure - H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] - H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips} - H10W 90/722: {between stacked chips} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - B81C: PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS (making microcapsules or microballoons B01J13/02; processes or apparatus specially adapted for the manufacture or treatment of piezoelectric, electrostrictive or magnetostrictive elements per se H10N30/01) - B81B: MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES (piezoelectric, electrostrictive or magnetostrictive elements per se H10N30/00, H10N35/00) ## Abstract Provided is a wafer level packaging. The packaging includes a first semiconductor wafer having a transistor device and a first bonding layer that includes a first material. The packaging includes a second semiconductor wafer having a second bonding layer that includes a second material different from the first material, one of the first and second materials being aluminum-based, and the other thereof being titanium-based. Wherein a portion of the second wafer is diffusively bonded to the first wafer through the first and second bonding layers. ## Claims ### Claim 1 A method of packaging, comprising: providing a first wafer, wherein the first wafer contains a plurality of transistors and an interconnect structure having a plurality of metal layers that each contain a plurality of metal lines; providing a second wafer, wherein the second wafer contains a micro-electrical-mechanical system (MEMS) device and a plurality of bonding pads; and bonding the first wafer and the second wafer together through a metal diffusion process and in a manner such that the bonding pads of the second wafer are bonded to the interconnect structure of the first wafer. ### Claim 2 (depends on 1) The method of claim 1, wherein the metal diffusion process includes: a process temperature that is greater than approximately 300 degrees Celsius; a process pressure that is greater than approximately 10 kilo-newtons; and a process duration that is in a range from approximately 9 minutes to approximately 15 minutes. ### Claim 3 (depends on 1) The method of claim 1, wherein the bonding is performed such that the bonding pads of the second wafer are bonded to a subset of the metal lines in a top-most metal layer of the interconnect structure of the first wafer. ### Claim 4 (depends on 1) The method of claim 1, wherein: the bonding pads each have a first material composition; the meta lines each have a second material composition; and the first material composition is different from the second material composition. ### Claim 5 (depends on 4) The method of claim 4, wherein one of the first and second material compositions include aluminum, and wherein the other one of the first and second material compositions include titanium. ### Claim 6 (depends on 1) The method of claim 1, further comprising: annealing the first and second wafers after the bonding. ### Claim 7 (depends on 1) The method of claim 1, further comprising: after the bonding of the first wafer and the second wafer, bonding a capping layer to the first wafer in a manner such that the MEMS device is hermetically sealed therein. ### Claim 8 A method of packaging, comprising: providing a first wafer, wherein the first wafer contains a plurality of transistors and an interconnect structure having a plurality of metal layers; providing a second wafer, wherein the second wafer contains a through-silicon-via (TSV) and a bonding pad disposed on the TSV; and bonding, through a metal diffusion process, the bonding pad of the second wafer to a top-most metal layer of the interconnect structure of the first wafer. ### Claim 9 (depends on 8) The method of claim 8, wherein the bonding is carried out using a metal diffusion process that includes: a process temperature that is greater than approximately 300 degrees Celsius; a process pressure that is greater than approximately 10 kilo-newtons; and a process duration that is in a range from approximately 9 minutes to approximately 15 minutes. ### Claim 10 (depends on 8) The method of claim 8, wherein the second wafer is a three-dimensional integrated circuit (3D-IC) wafer and includes a plurality of transistors. ### Claim 11 (depends on 8) The method of claim 8, wherein one of the interconnect structure and the bonding pad contains titanium, and the other one of the interconnect structure and the bonding pad contains aluminum. ### Claim 12 (depends on 8) The method of claim 8, further comprising: annealing the first wafer and the second wafer after the bonding. ### Claim 13 A method of packaging, comprising: providing a first semiconductor wafer and a second semiconductor wafer; forming a first bonding pad on the first wafer, the first bonding pad including a first bonding material; forming a second bonding pad on the second wafer, the second bonding pad including a second material different from the first material, one of the first and second materials being aluminum, and the other thereof being a titanium alloy; and bonding the first and second wafers together through the first and second bonding pads. ### Claim 14 (depends on 13) The method of claim 13, wherein the bonding is carried out using a metal diffusion process that includes: a process temperature that is greater than approximately 100 degrees Celsius; a process pressure that is greater than approximately 10 kilo-newtons; and a process duration that is in a range from approximately 3 minutes to approximately 300 minutes. ### Claim 15 (depends on 13) The method of claim 13, further including: after the bonding, annealing the first and second wafers at a temperature in a range from approximately 200 degrees Celsius to approximately 500 degrees Celsius for a duration in a range from approximately 0.5 hours to approximately 6 hours. ### Claim 16 (depends on 13) The method of claim 13, wherein: the forming one of the first and second bonding pads having the titanium alloy is carried out using a process selected from the group consisting of: physical vapor deposition, chemical vapor deposition, evaporation, electron beam gun, ion beam, energy beam, and plating; and the titanium alloy has a chemical composition of TixAlyCuz, x, y, and z each being in a range from 0 to 100. ### Claim 17 (depends on 13) The method of claim 13, further including: providing a third wafer; forming a third bonding pad on the first wafer, the third bonding pad including a third material; forming a fourth bonding pad on the third wafer, the fourth bonding pad having a fourth material different from the third material, one of the third and fourth materials being aluminum, and the other thereof being a titanium alloy; and after the bonding the first and second wafers, bonding the first and third wafers together through the third and fourth bonding pads. ### Claim 18 (depends on 17) The method of claim 17, wherein: the first wafer has a transistor; the second wafer has a micro-electrical-mechanical system (MEMS) device; and the third wafer is a capping layer. ### Claim 19 (depends on 13) The method of claim 13, wherein: the providing the first wafer is carried out in a manner so that the first wafer has an interconnect structure that includes a plurality of metal interconnect features; and the forming the first bonding pad is carried out in a manner so that the first bonding pad is one of the metal interconnect features. ### Claim 20 (depends on 13) The method of claim 13, wherein: the providing the second wafer is carried out in a manner so that the second wafer includes a through-silicon via (TSV); and the forming the second bonding pad is carried out in a manner so that the second bonding pad is electrically coupled to the TSV.