# US 2014/0154840 A1 · Chip package and method for forming the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0154840 A1 - Document ID: US20140154840A1 - Status: Published application - Kind: A1 - Application number: 14/173,340 - Filed: 2014-02-05 - Published: 2014-06-05 - Earliest claimed: 2011-01-03 - Assignees: Xintec Inc. - Applicants: Xintec Inc. - Inventors: Shu-Ming CHANG; Tsang-Yu LIU; Yen-Shih HO - Web page: https://patentgrep.com/patent/US20140154840A1 ## CPC - H10W 90/00: Package configurations - B81C 1/00238: {Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 88/01: {Manufacture or treatment} - H10W 20/023: {the interconnections being through-semiconductor vias} - H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes} - H10W 20/0242: {comprising etching via holes from the back sides of the chips, wafers or substrates} - H10W 20/216: {characterised by dielectric material at least partially filling the via holes, e.g. covering the through-semiconductor vias in the via holes} - H10W 76/60: Seals - B81C 2203/0785: Transfer and j oin technology, i.e. forming the electronic processing unit and the micromechanical structure on separate substrates and joining the substrates - B81C 2203/0792: Forming interconnections between the electronic processing unit and the micromechanical structure - H10W 70/65: Shapes or dispositions of interconnections - H10W 72/01935: {by plating, e.g. electroless plating or electroplating} - H10W 72/01938: {in gaseous form, e.g. by CVD or PVD} - H10W 72/0198: {batch processes} - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 72/227: {Multiple bumps having different sizes} - H10W 72/242: {relative to the surface, e.g. recessed, protruding} - H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10W 72/248: {Top-view layouts, e.g. mirror arrays} - H10W 72/263: {Providing mechanical bonding or support, e.g. dummy bumps} - H10W 72/267: {Multiple bump connectors having different functions} - H10W 72/29: Bond pads specially adapted therefor - H10W 72/856: {Bump connectors and die-attach connectors (bumps embedded in underfills H10W74/15)} - H10W 72/922: {Bond pads being integral with underlying chip-level interconnections} - H10W 72/932: {Plan-view shape, i.e. in top view} - H10W 72/9415: {relative to the surface, e.g. recessed, protruding} - H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu} - H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips} - H10W 90/722: {between stacked chips} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - B81C: PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS (making microcapsules or microballoons B01J13/02; processes or apparatus specially adapted for the manufacture or treatment of piezoelectric, electrostrictive or magnetostrictive elements per se H10N30/01) - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract An embodiment of the invention provides a chip package which includes: a first chip; a second chip disposed on the first chip; a hole extending from a surface of the first chip towards the second chip; a conducting layer disposed on the surface of the first chip and extending into the hole and electrically connected to a conducting region or a doped region in the first chip; and a support bulk disposed between the first chip and the second chip, wherein the support bulk substantially and/or completely covers a bottom of the hole. ## Claims ### Claim at position 1 1-12. (canceled) ### Claim 13 A method for forming a chip package, comprising: providing a first substrate; forming a support bulk on a surface of the first substrate; providing a second substrate; bonding the second substrate on the surface of the first substrate; removing a portion of the first substrate from a second surface of the first substrate to form a hole extending towards the support bulk on the first substrate, wherein the support bulk substantially and/or completely covers a bottom of the hole; and forming a conducting layer on the second surface of the first substrate, wherein the conducting layer extends into the hole to electrically connect to a conducting region or a doped region in the first substrate. ### Claim 14 (depends on 13) The method for forming a chip package as claimed in claim 13, further comprising: forming a protection layer on the second surface of the first substrate, wherein the protection layer has an opening exposing a portion of the conducting layer; and forming a conducting bump on the exposed conducting layer. ### Claim 15 (depends on 13) The method for forming a chip package as claimed in claim 13, further comprising dicing the first substrate and the second substrate to form at least a chip package. ### Claim 16 (depends on 13) The method for forming a chip package as claimed in claim 13, further comprising: forming a connection bulk on a surface of the second substrate; and bonding the first substrate and the second substrate by the connection bulk. ### Claim 17 (depends on 16) The method for forming a chip package as claimed in claim 16, wherein the connection bulk directly bonds with the support bulk. ### Claim 18 (depends on 16) The method for forming a chip package as claimed in claim 16, further comprising disposing at least a seal ring structure between the first substrate and the second substrate, wherein the seal ring structure surrounds a device region on the first substrate and/or the second substrate. ### Claim 19 (depends on 18) The method for forming a chip package as claimed in claim 18, wherein the seal ring structure is formed in a step by directly bonding the connection bulk with the support bulk. ### Claim 20 (depends on 13) The method for forming a chip package as claimed in claim 13, further comprising thinning the first substrate before the hole is formed. ### Claim 21 (depends on 13) The method for forming a chip package as claimed in claim 13, further comprising disposing at least an auxiliary support structure between the first substrate and the second substrate. ### Claim 22 (depends on 13) The method for forming a chip package as claimed in claim 13, wherein the first substrate and the second substrate are two semiconductor substrates. ### Claim 23 (depends on 22) The method for forming a chip package as claimed in claim 22, further comprising disposing a wafer periphery seal ring structure between the first substrate and the second substrate, wherein the wafer periphery seal ring structure, the first substrate, and the second substrate together form a cavity.