# US 2014/0154839 A1 · Method of manufacturing chip-stacked semiconductor package

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- Number: US 2014/0154839 A1
- Document ID: US20140154839A1
- Status: Published application
- Kind: A1
- Application number: 14/093,853
- Filed: 2013-12-02
- Published: 2014-06-05
- Earliest claimed: 2011-05-02
- Assignees: Samsung Electronics Co., Ltd.
- Inventors: Jung-seok Ahn; Dong-hyeon Jang; Ho-geon Song; Sung-jun Im; Chang-seong Jeon; Teak-hoon Lee; Sang-sick Park
- Web page: https://patentgrep.com/patent/US20140154839A1

## CPC

- H10W 90/00: Package configurations
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0245: {comprising use of blind vias during the manufacture}
- H10W 20/0249: {wherein the through-semiconductor via protrudes from backsides of the chips, wafers or substrates during the manufacture}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/2134: {TSVs extending from the semiconductor wafer into back-end-of-line layers}
- H10W 74/014: {using batch processing}
- H10P 72/7416: {used during dicing or grinding}
- H10P 72/744: {Details of chemical or physical process used for separating the auxiliary support from a device or a wafer}
- H10W 72/01204: {using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates}
- H10W 72/01935: {by plating, e.g. electroless plating or electroplating}
- H10W 72/0198: {batch processes}
- H10W 72/072: {of bump connectors}
- H10W 72/07207: {Temporary substrates, e.g. removable substrates}
- H10W 72/07254: {changes in dispositions}
- H10W 72/073: {of die-attach connectors}
- H10W 72/074: {of anisotropic conductive adhesives}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/325: {Die-attach connectors having a filler embedded in a matrix}
- H10W 72/353: {not comprising solid metals or solid metalloids, e.g. ceramics}
- H10W 72/354: {comprising polymers}
- H10W 72/9223: {with redistribution layers [RDL]}
- H10W 72/9226: {with via interconnections}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 74/147: {the encapsulations being multilayered}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/28: the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method of manufacturing a chip-stacked semiconductor package, the method including preparing a base wafer including a plurality of first chips each having a through-silicon via (TSV); bonding the base wafer including the plurality of first chips to a supporting carrier; preparing a plurality of second chips; forming stacked chips by bonding the plurality of second chips to the plurality of first chips; sealing the stacked chips with a sealing portion; and separating the stacked chips from each other.

## Claims

### Claim at position 1

1-20. (canceled)

### Claim 21

A method of manufacturing a chip-stacked semiconductor package, the method comprising:
providing a base wafer including a plurality of first chips each having a through-silicon via (TSV) and a first connection unit including a bump pad and a bump electrically connected to the through-silicon via (TSV);
bonding the base wafer including the plurality of first chips to a supporting carrier and covering the first connection unit with the supporting carrier;
providing a plurality of second chips; and
forming stacked chips by bonding the plurality of second chips to the plurality of first chips.

### Claim 22 (depends on 21)

New) The method of claim 21, further comprising, sealing the stacked chips with a sealing portion and separating the stacked chips from each other.

### Claim 23 (depends on 21)

The method of claim 21, further comprising, forming a protection layer and a conductive pad connected to the TSV on the base wafer and bonding a non-conductive film (NCF) or an anisotropic conductive film (ACF) to the protection layer and the conductive pad, and the forming of the stacked chips comprises bonding the plurality of second chips to the plurality of first chips through the NCF or the ACF.

### Claim 24 (depends on 21)

The method of claim 21, further comprising, filling a connection portion between the first chips and the second chips with an underfill.

### Claim 25 (depends on 21)

The method of claim 21, wherein, when the plurality of second chips are bonded to the plurality of first chips, at least two second chips are stacked on one first chip to provide stacked chips each comprising at least three chips.

### Claim 26 (depends on 21)

The method of claim 21, wherein the base wafer is prepared by a method comprising:
providing a semiconductor substrate having a first surface and a second surface opposite the first surface;
forming the TSV through the semiconductor substrate;
exposing the TSV to the second surface; and
forming a protection layer and a conductive pad connected to the TSV on the second surface,
wherein, in the bonding of the base wafer, the first connection unit of the first chip faces the supporting carrier.

### Claim 27 (depends on 21)

The method of claim 21, wherein the plurality of second chips each comprise a TSV.

### Claim 28 (depends on 21)

The method of claim 21, wherein each of the plurality of second chips comprises a second connection unit electrically connected to an integrated circuit layer thereof,
wherein, in the forming of the stacked chips, the second connection unit is electrically connected to the TSV.

### Claim 29 (depends on 22)

The method of claim 22, further comprising, before the separating of the stacked chips, exposing upper surfaces of the second chips by grinding an upper portion of the sealing portion.

### Claim 30 (depends on 29)

The method of claim 29, further comprising: after the exposing of the upper surfaces of the second chips,
removing the supporting carrier;
bonding a supporting substrate to the upper portion of the sealing portion; and
performing an electrical die sort (EDS) test for the stacked chips.

### Claim 31 (depends on 29)

New) The method of claim 29, further comprising: after the separating of the stacked chips,
removing the supporting substrate; and
mounting a separated stacked chip on a main chip.

### Claim 32 (depends on 31)

The method of claim 31, wherein a second TSV and a third connection unit connected to the second TSV are formed in the main chip, and the main chip is mounted on a board substrate through the third connection unit.

### Claim 33

A method of manufacturing a chip-stacked semiconductor package, the method comprising:
preparing a base wafer including a plurality of first chips each having a first size defined by a first length and a first width, each of the plurality of first chips having a through-silicon via (TSV) and a first connection unit including a bump pad and a bump electrically connected to the through-silicon via (TSV);
bonding the base wafer to a supporting carrier and covering the first connection unit with the supporting carrier; and
forming stacked chips by bonding a plurality of second chips to the plurality of first chips, the plurality of second chips each having a second size defined by a second length and a second width, that are shorter and narrower than the first length and the first width, respectively.

### Claim 34 (depends on 33)

The method of claim 33, further comprising, sealing the stacked chips with a sealing portion; and separating the stacked chips from each other by sawing the base wafer and the sealing portion exposing one or more sides of each of the first chips and one or more sides of each of the second chips.

### Claim 35 (depends on 34)

The method of claim 34, wherein after separating the stacked chips from each other the sealing portion remains to cover a connection portion between the first chips and the second chips and the sides of the second chips.

### Claim 36 (depends on 34)

The method of claim 34, wherein the base wafer and the sealing portion are sawed along lines so as to separate each of the first chips and exposing a sealing portion covering the sides of each of the second chips.

### Claim 37 (depends on 34)

The method of claim 34, wherein the base wafer and the sealing portion are sawed along lines so as to separate each of the second chips and exposing the sides of the first chips and the second chips.

### Claim 38

A method of manufacturing a chip-stacked semiconductor package, the method comprising:
preparing a base wafer including a plurality of first chips each having a through silicon via (TSV) by a method including:
providing a semiconductor substrate having a first surface and a second surface opposite the first surface;
forming the TSV through the semiconductor substrate;
exposing the TSV to the second surface; and
forming a protection layer and a conductive pad connected to the TSV on the second surface,
wherein, in the bonding of the base wafer, the first connection unit of the first chip faces the supporting carrier; and
forming stacked chips by bonding one of a plurality of second chips to each of the plurality of first chips.

### Claim 39 (depends on 38)

The method of claim 38, wherein the preparing of the base wafer further comprises:
bonding a non-conductive film (NCF) or an anisotropic conductive film (ACF) to the protection layer and the conductive pad, wherein the forming of the stacked chips comprises bonding the plurality of second chips to the plurality of first chips through the NCF or the ACF.

### Claim 40 (depends on 38)

The method of claim 38, wherein each of the plurality of second chips comprises a second connection unit electrically connected to an integrated circuit layer thereof; and wherein the second connection unit is electrically connected to the TSV.