# US 2014/0154833 A1 · Manufacturing method for detection apparatus

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- Number: US 2014/0154833 A1
- Document ID: US20140154833A1
- Status: Published application
- Kind: A1
- Application number: 14/085,993
- Filed: 2013-11-21
- Published: 2014-06-05
- Earliest claimed: 2012-12-03
- Assignees: Canon Kabushiki Kaisha
- Applicants: Canon Kabushiki Kaisha
- Inventors: Hiroshi Wayama; Minoru Watanabe; Keigo Yokoyama; Masato Ofuji; Jun Kawanabe; Kentaro Fujiyoshi
- Web page: https://patentgrep.com/patent/US20140154833A1

## CPC

- H10F 39/1898: {Indirect radiation image sensors, e.g. using luminescent members}
- H10F 39/802: {Geometry or disposition of elements in pixels, e.g. address-lines or gate electrodes}
- H10F 39/8023: {Disposition of the elements in pixels, e.g. smaller elements in the centre of the imager compared to larger elements at the periphery}
- H10F 39/803: {Pixels having integrated switching, control, storage or amplification elements}
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION

## Abstract

A manufacturing method for a detection apparatus is provided. The method includes depositing a first impurity semiconductor layer and a first intrinsic semiconductor layer in this order on a plurality of first electrodes arranged in an array above a substrate. The method also includes patterning the first intrinsic semiconductor layer and the first impurity semiconductor layer and thereby dividing the first intrinsic semiconductor layer and the first impurity semiconductor layer so as to cover each of the plurality of first electrodes separately. The method further includes depositing a second intrinsic semiconductor layer on the patterned first intrinsic semiconductor layer.

## Claims

### Claim 1

A manufacturing method for a detection apparatus comprising:
a first deposition step of depositing a first impurity semiconductor layer and a first intrinsic semiconductor layer in this order on a plurality of first electrodes arranged in an array above a substrate;
a patterning step of patterning the first intrinsic semiconductor layer and the first impurity semiconductor layer and thereby dividing the first intrinsic semiconductor layer and the first impurity semiconductor layer so as to cover each of the plurality of first electrodes separately; and
a second deposition step of depositing a second intrinsic semiconductor layer on the patterned first intrinsic semiconductor layer.

### Claim 2 (depends on 1)

The method according to claim 1, wherein a second impurity semiconductor layer is deposited on the second intrinsic semiconductor layer in the second deposition step.

### Claim 3 (depends on 2)

The method according to claim 2, further comprising a second electrode forming step of forming a second electrode on the second impurity semiconductor layer.

### Claim 4 (depends on 1)

The method according to claim 1, wherein in the first deposition step, after the first impurity semiconductor layer is deposited, the first intrinsic semiconductor layer is deposited without exposure to the atmosphere.

### Claim 5 (depends on 1)

The method according to claim 1, wherein in the second deposition step, after the second intrinsic semiconductor layer is deposited, the second impurity semiconductor layer is deposited without exposure to the atmosphere.

### Claim 6 (depends on 1)

The method according to claim 1, further comprising a step of removing an oxide film on a surface of the first intrinsic semiconductor layer by hydrofluoric acid treatment before the second deposition step.

### Claim 7 (depends on 1)

The method according to claim 1, further comprising a step of forming a plurality of transistors above the substrate and forming an insulating layer configured to cover the plurality of transistors before forming the first electrodes, wherein
the plurality of first electrodes is formed above the insulating layer and electrically connected to the plurality of transistors.

### Claim 8 (depends on 7)

The method according to claim 7, wherein:
the insulating layer is an organic insulating layer;
the method further comprises a step of forming an inorganic insulating layer configured to cover a part of the insulating layer which is not covered by the plurality of first electrodes before the first deposition step; and
the inorganic insulating layer functions as an etching stopper layer when the first impurity semiconductor layer is patterned.

### Claim 9 (depends on 8)

The method according to claim 8, wherein:
the inorganic insulating layer is formed so as to cover edges of the plurality of first electrodes; and
in the patterning step, the first impurity semiconductor layer is patterned so as to cover edges of the inorganic insulating layer.

### Claim 10 (depends on 1)

The method according to claim 1, wherein in the patterning step, the first impurity semiconductor layer is patterned so as to cover edges of the plurality of first electrodes.

### Claim 11 (depends on 1)

The method according to claim 1, wherein the first intrinsic semiconductor layer and the second intrinsic semiconductor layer are equal to each other in thickness.