# US 2014/0154823 A1 · Manufacturing method of tft array substrate > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0154823 A1 - Document ID: US20140154823A1 - Status: Published application - Kind: A1 - Application number: 13/704,156 - Filed: 2012-11-14 - Published: 2014-06-05 - Earliest claimed: 2011-12-31 - Assignees: Boe Technology Group Co., Ltd. - Applicants: Boe Technology Group Co., Ltd. - Inventors: Xiang Liu; Jianshe Xue - Web page: https://patentgrep.com/patent/US20140154823A1 ## CPC - H10D 86/0231: {using masks, e.g. half-tone masks} - H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate} - H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO} - H10D 86/60: wherein the TFTs are in active matrices - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract Embodiments of the invention provide a manufacturing method of a TFT array substrate. The TFT array substrate is formed to comprise a plurality of scanning lines, a plurality of data lines and a plurality of pixel units defined by intersecting these scanning lines and these data lines with each other. Each of the pixel units comprises a TFT and a pixel electrode. The TFT is formed to comprise a gate electrode, a gate insulating layer, a metal oxide semiconductor layer used as an active layer, an etch stopping layer formed on a portion of the surface of the metal oxide semiconductor layer, a source electrode and a drain electrode. In this method, the metal oxide semiconductor layer, the source electrode and the drain electrode are formed by a same patterning process. ## Claims ### Claim 1 A manufacturing method of a TFT array substrate, the TFT array substrate being formed to comprise a plurality of scanning lines, a plurality of data lines and a plurality of pixel units defined by intersecting these scanning lines and these data lines with each other, each of the pixel units comprising a TFT and a pixel electrode, the TFT being formed to comprise: a gate electrode, a gate insulating layer, a metal oxide semiconductor layer used as an active layer, an etch stopping layer formed on a portion of the surface of the metal oxide semiconductor layer, a source electrode and a drain electrode, wherein the metal oxide semiconductor layer, the source electrode and the drain electrode are formed by a same patterning process. ### Claim 2 (depends on 1) The manufacturing method according to claim 1, wherein during a patterning process for forming the source electrode and the drain electrode, the patterns of the source electrode, the drain electrode and the etch stopping layer are used as a mask to form the metal oxide semiconductor layer, so that the metal oxide semiconductor layer is simultaneously formed in the patterning process for farming the source electrode and the drain electrode. ### Claim 3 (depends on 2) The manufacturing method according to claim 2, wherein the method comprises the following steps: step S1: forming a gate metal film on a substrate, and forming the gate electrode and the scanning lines by a patterning process; step S2: forming the gate insulating layer on the substrate after step S1, depositing a metal oxide semiconductor film on the gate insulating layer, depositing an etch stopping film on the metal oxide semiconductor film, and forming the etch stopping layer by a patterning process; step S3: depositing a source/drain metal film on the substrate after step S2, and forming the source electrode, the drain electrode, the data lines and the metal oxide semiconductor layer by a patterning process; step S4: forming a protective layer on the substrate after step S3, and forming a contact via hole by a patterning process; and step S5: depositing a transparent conductive film on the substrate after step S4, and forming the pixel electrode by a patterning process, the pixel electrode being connected to the drain electrode by the contact via hole. ### Claim 4 (depends on 3) The manufacturing method according to claim 3, wherein all patterning processes in steps S1 to S5 employ normal masks. ### Claim 5 (depends on 1) The manufacturing method according to claim 1, wherein the source electrode is formed such that one end thereof is provided on the etch stopping layer and the other end thereof is provided on the metal oxide semiconductor layer; and wherein the drain electrode is formed such that one end thereof opposite to the source electrode is provided on the etch stopping layer and the other end thereof is provided on the metal oxide semiconductor layer. ### Claim 6 (depends on 1) The manufacturing method according to claim 1, wherein, the metal oxide semiconductor layer is made of amorphous IGZO, HIZO, IZO, a-InZnO, a-InZnO, ZnO:F, In2O3:Sn, In2O3:Mo, Cd2SnO4, ZnO:Al, TiO2:Nb, Cd—Sn—O. ### Claim 7 (depends on 1) The manufacturing method according to claim 1, wherein the gate insulating layer has a double-layer structure, and wherein in the double-layer structure of the gate insulating layer, a layer which contacts the metal oxide semiconductor layer is a protective layer, and a layer which does not contact the metal oxide semiconductor layer is an insulating layer. ### Claim 8 (depends on 7) The manufacturing method according to claim 7, wherein the protective layer is made of SiOx and is formed by a low-speed deposition method. ### Claim 9 (depends on 7) The manufacturing method according to claim 7, wherein the insulating layer is made of SiNx and is formed by a high-speed deposition method. ### Claim 10 (depends on 1) The manufacturing method according to claim 1, wherein the etch stopping layer has a double-layer structure, and wherein in the double-structure layer of the etch stopping layer, a layer which contacts the metal oxide semiconductor layer is a protective layer and a layer which does not contact the metal oxide semiconductor layer is a barrier layer. ### Claim 11 (depends on 10) The manufacturing method according to claim 10, wherein the protective layer is made of SiOx and is formed by a low-speed deposition method. ### Claim 12 (depends on 10) The manufacturing method according to claim 10, wherein the barrier layer is made of SiNx and is formed by a high-speed deposition method. ### Claim 13 (depends on 1) The manufacturing method according to claim 1, wherein the gate insulating layer has a single-layer structure and is made of silicon oxide, silicon nitride or silicon oxynitride. ### Claim 14 (depends on 1) The manufacturing method according to claim 1, wherein the etch stopping layer has a single-layer structure and is made of silicon oxide, silicon nitride or silicon oxynitride.