# US 2014/0153682 A1 · Digital phase detector with zero phase offset

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- Number: US 2014/0153682 A1
- Document ID: US20140153682A1
- Status: Published application
- Kind: A1
- Application number: 14/150,508
- Filed: 2014-01-08
- Published: 2014-06-05
- Earliest claimed: 2011-09-23
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Daniel M. Dreps; Kyu-hyoun Kim; Glen A. Wiedemeier
- Web page: https://patentgrep.com/patent/US20140153682A1

## CPC

- H03L 7/0814: {the phase shifting device being digitally controlled}
- H03L 7/085: concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00)
- H03L 7/089: the phase or frequency detector generating up-down pulses (H03L7/087 takes precedence)
- H04L 7/0037: {Delay of clock signal}
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

An embodiment of the invention comprises a digital phase detector with substantially zero phase offset. The digital phase detector receives a clock signal and a reference clock signal and provides a phase indicator signal to identify whether the clock signal leads or lags the reference clock signal. An embodiment of the invention comprises a method that adds substantially zero phase offset in processing an input clock signal and a delayed clock signal to generate a control signal. The control signal is processed in a variable delay line to generate the delayed clock signal. In an embodiment, a first processor comprises a delay locked loop having a digital phase detector, the digital phase detector comprising a first differential sense amplifier cross-coupled to a second differential sense amplifier, the digital phase detector receiving a clock signal and generating one or more delayed clock signals, a control signal, and a gated data signal.

## Claims

### Claim at position 1

1-16. (canceled)

### Claim 17

A communication system comprising:
a first processor comprising a delay locked loop having a digital phase detector, the digital phase detector comprising a first differential sense amplifier cross-coupled to a second differential sense amplifier, the digital phase detector to receive a clock signal and to generate one or more delayed clock signals, a control signal, and a gated data signal; and
a second processor coupled to the first processor, the second processor to receive the control signal and the gated data signal.

### Claim 18 (depends on 17)

The communication system of claim 17, wherein the first processor is included in a mobile communication system.

### Claim 19 (depends on 17)

The communication system of claim 17, wherein the second processor is included in a cell station.

### Claim 20 (depends on 17)

The communication system of claim 17, wherein the digital phase detector has substantially zero phase offset.