# US 2014/0153635 A1 · Method, computer program product, and system for multi-threaded video encoding > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0153635 A1 - Document ID: US20140153635A1 - Status: Published application - Kind: A1 - Application number: 13/706,302 - Filed: 2012-12-05 - Published: 2014-06-05 - Earliest claimed: 2012-12-05 - Assignees: NVIDIA Corporation - Applicants: Nvidia Corporation - Inventors: Guanjun Zhang; Haixia Shi; Olivier Lapicque; Xiaohua Yang - Web page: https://patentgrep.com/patent/US20140153635A1 ## CPC - H04N 19/436: using parallelised computational arrangements - H04N 19/423: characterised by memory arrangements (H04N19/433 takes precedence) - H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION ## Abstract A method, computer program product, and system are provided for multi-threaded video encoding. The method includes the steps of generating a set of motion vectors in a hardware video encoder based on a current frame of a video stream and a reference frame of the video stream, dividing the current frame into a number of slices, encoding each slice of the current frame based on the set of motion vectors, and combining the encoded slices to generate an encoded bitstream. ## Claims ### Claim 1 A method comprising: generating a set of motion vectors in a hardware video encoder based on a current frame of a video stream and a reference frame of the video stream; dividing the current frame into a number of slices; encoding each slice of the current frame based on the set of motion vectors; and combining the encoded slices to generate an encoded bitstream. ### Claim 2 (depends on 1) The method of claim 1, wherein the encoded bitstream is a VC-1 compatible bitstream. ### Claim 3 (depends on 1) The method of claim 1, further comprising: generating a master thread configured to combine the encoded slices; and generating two or more child threads, wherein each child thread is configured to encode a particular slice of the current frame allocated to the child thread. ### Claim 4 (depends on 3) The method of claim 3, wherein the master thread and the two or more child threads are configured to be executed in a parallel processing unit. ### Claim 5 (depends on 4) The method of claim 4, wherein the hardware video encoder and the parallel processing unit are included in a system-on-chip (SoC). ### Claim 6 (depends on 3) The method of claim 3, wherein each child thread of the two or more child threads is configured to generate a byte-aligned encoded slice by encoding motion vectors and quantized transform coefficients using variable length codes to generate a portion of the encoded bitstream. ### Claim 7 (depends on 6) The method of claim 6, wherein each child thread of the two or more child threads is configured to add one or more stuffing bits to the portion of the encoded bitstream generated by that child thread such that the portion is byte-aligned. ### Claim 8 (depends on 1) The method of claim 1, further comprising transmitting a copy of the current frame to the hardware video encoder. ### Claim 9 (depends on 8) The method of claim 8, wherein a driver receives instructions from an application and is configured to transmit the copy of the current frame to the hardware video encoder. ### Claim 10 (depends on 9) The method of claim 9, wherein the hardware video encoder notifies the driver that the set of motion vectors is available, and wherein the driver is configured to generate one or more threads for execution by a parallel processing unit to encode each slice of the current frame based on the set of motion vectors and combine the encoded slices to generate the encoded bitstream. ### Claim 11 (depends on 1) The method of claim 1, wherein the hardware video encoder is configured to implement an H.264/MPEG Part 10 (Advanced Video Coding) standard for video compression. ### Claim 12 (depends on 11) The method of claim 11, wherein the hardware video encoder includes a motion estimation engine that is configured to generate the set of motion vectors. ### Claim 13 (depends on 1) The method of claim 1, wherein the hardware video encoder is configured to implement an MPEG-2 standard for video compression. ### Claim 14 A non-transitory computer-readable storage medium storing instructions that, when executed by a processor, cause the processor to perform steps comprising: generating a set of motion vectors in a hardware video encoder based on a current frame of a video stream and a reference frame of the video stream; dividing the current frame into a number of slices; encoding each slice of the current frame based on the set of motion vectors; and combining the encoded slices to generate an encoded bitstream ### Claim 15 (depends on 14) The non-transitory computer-readable storage medium of claim 14, wherein the encoded bitstream is a VC-1 compatible bitstream. ### Claim 16 (depends on 14) The non-transitory computer-readable storage medium of claim 14, the steps further comprising: generating a master thread configured to combine the encoded slices; and generating two or more child threads, wherein each child thread is configured to encode a particular slice of the current frame allocated to the child thread. ### Claim 17 A system comprising: a hardware video encoder configured to generate a set of motion vectors based on a current frame of a video stream and a reference frame of the video stream; and a processor coupled to the hardware video encoder and configured to: divide the current frame into a number of slices, encode each slice of the current frame based on the set of motion vectors, and combine the encoded slices to generate an encoded bitstream. ### Claim 18 (depends on 17) The system of claim 17, wherein the encoded bitstream is a VC-1 compatible bitstream. ### Claim 19 (depends on 17) The system of claim 17, wherein the hardware video encoder is configured to implement an H.264/MPEG Part 10 (Advanced Video Coding) standard for video compression ### Claim 20 (depends on 17) The system of claim 17, wherein the processor is a graphics processing unit, and wherein the processor is further configured to execute a master thread configured to combine the encoded slices and two or more child threads, wherein each child thread is configured to encode a particular slice of the current frame allocated to the child thread.