# US 2014/0153631 A1 · Methods and circuits for asymmetric distribution of channel equalization between devices

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- Number: US 2014/0153631 A1
- Document ID: US20140153631A1
- Status: Published application
- Kind: A1
- Application number: 13/911,363
- Filed: 2013-06-06
- Published: 2014-06-05
- Earliest claimed: 2006-12-05
- Assignees: Rambus Inc.
- Applicants: Rambus Inc.
- Inventors: Jared L. Zerbe; Fariborz Assaderaghi; Brian S. Leibowitz; Hae-Chang Lee; Jihong Ren; Qi Lin
- Web page: https://patentgrep.com/patent/US20140153631A1

## CPC

- H04L 25/03343: {Arrangements at the transmitter end}
- H01J 37/00: Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof (H01J33/00, H01J40/00, H01J41/00, H01J47/00, H01J49/00 take precedence)
- H04L 25/03057: {with a recursive structure (H04L25/03031 takes precedence)}
- H04L 25/0307: {using blind adaptation}
- H04L 25/03885: {adaptive}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10P 50/283: {by chemical means}
- H10P 50/73: {using masks for insulating materials}
- H10P 72/0421: {for drying etching}
- H10P 72/722: {Details of electrostatic chucks}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/083: {the openings being via holes penetrating underlying conductors}
- H04L 2025/03356: {Baseband transmission}
- H04L 2025/03433: {characterised by equaliser structure}
- H04L 2025/03617: {Time recursive algorithms (H04L2025/03643 takes precedence)}
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- H01J: ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS (spark-gaps H01T; electric arc lamps H05B31/00; particle accelerators H05H)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

## Claims

### Claim 1

A first integrated circuit to communicate with a second integrated circuit over at least one conductive path, the first integrated circuit comprising:
a transmitter to transmit information from the first integrated circuit to the second integrated circuit over a first conductive path, the transmitter including a transmit equalizer;
a receiver to receive information from the second integrated circuit over one of the first conductive path, or a second conductive path; and
a circuit to generate equalization settings for the transmit equalizer responsive to inter-symbol interference affecting the transmission of the information transmitted to the first integrated circuit from the second integrated circuit.