# US 2014/0153590 A1 · Method and apparatus for transmitting data

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2014/0153590 A1
- Document ID: US20140153590A1
- Status: Published application
- Kind: A1
- Application number: 14/171,921
- Filed: 2014-02-04
- Published: 2014-06-05
- Earliest claimed: 2011-03-01
- Assignees: Freescale Semiconductor, Inc.
- Inventors: Paul Kelleher; Michael O'Brien; Conor O'Keeffe
- Web page: https://patentgrep.com/patent/US20140153590A1

## CPC

- H04W 56/0045: {compensating for timing error by altering transmission time}
- H04B 1/40: Circuits
- H04B 15/02: Reducing interference from electric apparatus by means located at or near the interfering apparatus
- H04B 2215/067: by modulation dispersion
- H04W: WIRELESS COMMUNICATION NETWORKS (broadcast communication H04H; communication systems using wireless links for non-selective communication, e.g. wireless extensions H04M1/72)
- H04B: TRANSMISSION

## Abstract

A semiconductor device comprising interface logic for transmitting data bursts across an interface. The interface logic is arranged to transmit bursts of data across the interface such that the start of a burst of data is substantially aligned with a symbol interval (SI) boundary. The interface logic is further arranged to apply an offset to the SI boundary at the start of the burst of data.

## Claims

### Claim 1

A method for transmitting data across an interface, the method comprising:
determining a first default symbol interval boundary;
transmitting a first burst of data across the interface at a time based upon the first default symbol interval boundary;
determining a second default symbol interval boundary;
transmitting a second burst of data across the interface, wherein the start of the second burst of data is substantially aligned with the second default symbol interval boundary;
determining a third default symbol interval boundary, the time between the first and second default symbol interval boundaries being substantially the same as the time between the second and third default interval boundaries; and
transmitting a third burst of data across the interface, wherein the start of the third burst of data is not substantially aligned with the third default symbol interval boundary.

### Claim 2 (depends on 1)

The method of claim 1 further comprising:
applying an offset of (+/−N*UI) to a default symbol interval boundary at the start of a burst of data, where UI equals a unit interval of a fixed amount of time, and N equals (K−1), where K equals a number of unit intervals in one symbol interval.

### Claim 3 (depends on 1)

The method of claim 1 further comprising:
receiving a unit interval timing signal;
receiving a symbol interval value; and
dividing the unit interval timing signal by the received symbol value to generate a symbol interval timing signal.

### Claim 4 (depends on 3)

The method of claim 3 further comprising:
applying an offset to the symbol interval timing signal before the start of a burst of data.

### Claim 5 (depends on 1)

The method of claim 1 wherein a substantially random offset determines the start of the second burst of data.

### Claim 6 (depends on 1)

The method of claim 1 further comprising:
receiving a unit interval timing signal; and
offsetting a transition between a sleep/stall state and a start of a burst of data by integer multiples of a period the first signal.

### Claim 7

A semiconductor device comprising:
an interconnect; and
interface logic coupled to the interconnect, the interface logic to determine a first default symbol interval boundary, to transmit a first burst of data across the interconnect at a time based upon the first default symbol interval boundary, to determine a second default symbol interval boundary, to transmit a second burst of data that is substantially aligned with the second default symbol interval boundary, to determine a third default symbol interval boundary, the time between the first and second default interval boundaries being substantially the same as the time between the second and third default interval boundaries, and to transmit a third burst of data that is not substantially aligned with the third default symbol interval boundary.

### Claim 8 (depends on 7)

The semiconductor device of claim 7 wherein the interface logic includes:
a data storage to store data received at the interface logic; and
a line driver coupled to the data storage and to the interconnect, the line driver to transmit the data stored in the data storage in the bursts.

### Claim 9 (depends on 7)

The semiconductor device of claim 7 wherein the interface logic is arranged to apply a substantially random offset to a default symbol interval boundary before the start of a burst of data.

### Claim 10 (depends on 7)

The semiconductor device of claim 7 wherein the interface logic is arranged to apply an offset to a default symbol interval boundary before the start of a burst of data in accordance with an offset sequence.

### Claim 11 (depends on 7)

The semiconductor device of claim 7 wherein the interface logic comprises:
timing logic to generate a symbol interval timing signal in accordance with which the transmission of each burst of data is substantially aligned, and the timing logic further to apply an offset to the symbol interval timing signal before the start of a burst of data.

### Claim 12 (depends on 11)

The semiconductor device of claim 11 wherein the timing logic comprises:
divider logic to receive a unit interval timing signal, to receive a symbol interval value, and to divide the unit interval timing signal by the received symbol value to generate the symbol interval timing signal.

### Claim 13 (depends on 12)

The semiconductor device of claim 12 wherein the timing logic further comprises:
offset generation logic to generate an offset value, wherein the offset value is applied to a default symbol interval value, the resulting symbol interval value being provided to the divider logic for generating the symbol interval timing signal.

### Claim 14 (depends on 7)

The semiconductor device of claim 7 wherein the interface logic comprises:
dither logic to receive a unit interval timing signal, and to offset a transition between a sleep/stall state and a start of a burst of data by integer multiples of unit intervals.

### Claim 15 (depends on 7)

The semiconductor device of claim 7 wherein the interface logic is arranged to apply an offset of (+/−N*UI) to a default symbol interval boundary at the start of a burst of data, where UI equals a unit interval of a fixed amount of time, and N equals (K−1), where K equals a number of unit intervals in one symbol interval.

### Claim 16

A non-transitory computer-readable storage element comprising executable program code for programming interface logic, the computer program product comprising program code for:
determining a first default symbol interval boundary;
transmitting a first burst of data across the interface at a time based upon the first default symbol interval boundary;
determining a second default symbol interval boundary;
transmitting a second burst of data across the interface, wherein the start of the second burst of data is substantially aligned with the second default symbol interval boundary;
determining a third default symbol interval boundary, the time between the first and second default symbol interval boundaries being substantially the same as the time between the second and third default interval boundaries; and
transmitting a third burst of data across the interface, wherein the start of the third burst of data is not substantially aligned with the third default symbol interval boundary.

### Claim 17 (depends on 16)

The non-transitory computer-readable storage element of claim 16 further comprising program code for:
applying an offset of (+/−N*UI) to a default symbol interval boundary at the start of a burst of data, where UI equals a unit interval of a fixed amount of time, and N equals (K−1), where K equals a number of unit intervals in one symbol interval.

### Claim 18 (depends on 16)

The non-transitory computer-readable storage element of claim 16 further comprising program code for:
receiving a unit interval timing signal;
receiving a symbol interval value; and
dividing the unit interval timing signal by the received symbol value to generate a symbol interval timing signal.

### Claim 19 (depends on 18)

The non-transitory computer-readable storage element of claim 18 further comprising program code for:
applying an offset to the symbol interval timing signal at the start of a burst of data.

### Claim 20 (depends on 16)

The non-transitory computer-readable storage element of claim 16 wherein a substantially random offset determines the start of the second burst of data.