# US 2014/0153352 A1 · Semiconductor device including plural chips stacked to each other

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- Number: US 2014/0153352 A1
- Document ID: US20140153352A1
- Status: Published application
- Kind: A1
- Application number: 14/175,839
- Filed: 2014-02-07
- Published: 2014-06-05
- Earliest claimed: 2011-01-17
- Assignees: PS4 Luxco S.a.r.l.
- Inventors: Homare Sato
- Web page: https://patentgrep.com/patent/US20140153352A1

## CPC

- G11C 11/408: Address circuits
- G06F 12/0207: {with multidimensional access, e.g. row/column, matrix}
- G06F 12/08: in hierarchically structured memory systems, e.g. virtual memory systems
- G11C 5/02: Disposition of storage elements, e.g. in the form of a matrix array
- G11C 11/4063: Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/217: {comprising ring-shaped isolation structures outside of the via holes}
- G06F 12/0223: {User address space allocation, e.g. contiguous or non contiguous base addressing}
- G11C 5/04: Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports
- G11C 8/12: Group selection circuits, e.g. for memory block selection, chip selection, array selection
- H10W 90/00: Package configurations
- H10W 90/722: {between stacked chips}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method for accessing a plurality of DRAM devices each having a plurality of banks, includes determining an operating mode for the plurality of DRAM devices, providing a chip selection address and a bank address with an active command to activate a first bank in a first one of the plurality of DRAM devices and, while the first bank in the first one of the plurality of DRAM devices is activated, one or more first banks in remaining DRAM devices of the plurality of DRAM devices are: not activated if the operating mode is determined to be a logical rank address mode, and possibly activated if the operating mode is determined to be a physical rank address mode, and subsequently providing at least a bank address with a column command to access the first bank in the first one of the plurality of DRAM devices.

## Claims

### Claim 1

A method for accessing a plurality of DRAM devices each having a plurality of banks, the plurality of DRAM devices being interconnected to receive common address and command signals, the method comprising:
determining an operating mode for the plurality of DRAM devices;
providing a chip selection address and a bank address with an active command to activate a first bank in a first one of the plurality of DRAM devices and, while the first bank in the first one of the plurality of DRAM devices is activated, one or more first banks in remaining DRAM devices of the plurality of DRAM devices are:
not activated if the operating mode is determined to be a logical rank address mode; and
possibly activated if the operating mode is determined to be a physical rank address mode; and
subsequently providing at least a bank address with a column command to access the first bank in the first one of the plurality of DRAM devices.

### Claim 2 (depends on 1)

The method as claimed in claim 1 wherein a chip selection address is also provided with the column command in the physical rank address mode.

### Claim 3 (depends on 1)

The method as claimed in claim 1 wherein a chip selection address is not provided with the column command in the logical rank address mode.

### Claim 4 (depends on 1)

The method as claimed in claim 1 wherein the operating mode is set in a mode register.

### Claim 5 (depends on 4)

The method as claimed in claim 4 wherein the operating mode is set in a nonvolatile memory.

### Claim 6 (depends on 5)

The method as claimed in claim 5 wherein the operating mode is set in a fuse.

### Claim 7 (depends on 1)

The method as claimed in claim 1 wherein the plurality of DRAM devices are provided in a stacked configuration connected by through silicon vias.

### Claim 8 (depends on 7)

The method as claimed in claim 7 wherein an interposer with external terminals is provided at a stack bottom.

### Claim 9 (depends on 1)

The method as claimed in claim 1 wherein a chip selection address is also provided with the column command in the physical rank address mode, and the chip selection address is compared to a specific chip address in each of the plurality of DRAM devices to determine the first one of the plurality of DRAM devices.

### Claim 10 (depends on 9)

The method as claimed in claim 9 wherein the specific chip address in each of the plurality of DRAM devices is determined through a cascaded connection of the plurality of DRAM devices.