# US 2014/0153348 A1 · Operation Scheme for Non-Volatile Memory > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0153348 A1 - Document ID: US20140153348A1 - Status: Published application - Kind: A1 - Application number: 13/690,299 - Filed: 2012-11-30 - Published: 2014-06-05 - Earliest claimed: 2012-11-30 - Assignees: Infineon Technologies AG - Applicants: Infineon Technologies AG - Inventors: Thomas Nirschl; Jan Otterstedt; Alexander Duch - Web page: https://patentgrep.com/patent/US20140153348A1 ## CPC - G11C 7/00: Arrangements for writing information into, or reading information out from, a digital store (G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413) - G11C 16/0425: {comprising cells containing a merged floating gate and select transistor} - G11C 16/3427: {Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written} - G11C 16/349: {Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A method of operating an integrated circuit includes determining at least one characteristic of at least one memory cell and conducting an operation for the at least one memory cell, wherein based on the at least one characteristic determined a disturbance for at least one additional memory cell is adjusted. ## Claims ### Claim 1 A method of operating an integrated circuit, the method comprising: determining at least one characteristic of at least one memory cell; and conducting an operation for the at least one memory cell, wherein based on the at least one characteristic determined a disturbance for at least one additional memory cell is adjusted. ### Claim 2 (depends on 1) The method according to claim 1, wherein the at least one characteristic comprises at least one usage characteristic that indicates a number of operations of the at least one memory cell. ### Claim 3 (depends on 1) The method according to claim 1, wherein the at least one memory cell and the at least one additional memory cell are electrically coupled. ### Claim 4 (depends on 1) The method according to claim 1, wherein the operation comprises at least one of: a read operation; a write operation; and an erase operation. ### Claim 5 (depends on 1) The method according to claim 1, wherein the disturbance for the at least one additional memory cell is adjusted by adjusting a disturb signal for the at least one additional memory cell. ### Claim 6 (depends on 5) The method according to claim 5, wherein the disturb signal comprises a disturb voltage applied between a first terminal and a second terminal of the at least one additional memory cell. ### Claim 7 (depends on 6) The method according to claim 6, wherein the first terminal is a control gate and the second terminal is a drain, a source or a well. ### Claim 8 (depends on 1) The method according to claim 1, wherein the at least one memory cell and the at least one additional memory cell share a well of the integrated circuit. ### Claim 9 (depends on 1) The method according to claim 1, wherein the at least one characteristic of the at least one memory cell is determined via a predefined parameter or based on access patterns to the at least one memory cell. ### Claim 10 (depends on 1) The method according to claim 1, wherein the at least one memory cell and the at least one additional memory cell are each organized in blocks or pages. ### Claim 11 (depends on 1) The method according to claim 1, wherein the at least one memory cell and the at least one additional memory cell are part of the same integrated circuit. ### Claim 12 (depends on 1) The method according to claim 1, wherein the integrated circuit comprises at least one non-volatile memory selected from the following group: EEPROM; floating gate NVM; PCRAM; CBRAM; nano-crystal NVM; MONOS; and TANOS. ### Claim 13 (depends on 1) The method according to claim 1, wherein the at least one characteristic of the at least one memory cell depends on the size or the usage of the at least one memory cell. ### Claim 14 (depends on 1) The method according to claim 1, wherein the at least one characteristic of the at least one memory cell is one of: a first characteristic indicating that the memory cell is rarely changed and thus rarely erased; and a second characteristic indicating that the memory cell is frequently changed and thus often accessed. ### Claim 15 (depends on 14) The method according to claim 14, wherein the operation is conducted with a low disturb voltage when the at least one memory cell is of the first characteristic,. ### Claim 16 (depends on 14) The method according to claim 14, wherein the operation is conducted with a high disturb voltage when the at least one memory cell is of the second characteristic,. ### Claim 17 (depends on 1) The method according to claim 1, wherein the operation comprises a read operation to determine whether the operation or an access was successful. ### Claim 18 (depends on 17) The method according to claim 17, wherein a subsequent operation is adjusted based on the success of the previous operation or access. ### Claim 19 (depends on 18) The method according to claim 18, wherein the subsequent operation is an iteration of the previous operation or the subsequent operation applies a different voltage and/or a different pulse length as the pervious operation. ### Claim 20 An integrated circuit, comprising: a non-volatile memory comprising a first memory portion and a second memory portion; and a controller configured to: determine at least one characteristic of the first memory portion; and conduct an operation for the first memory portion, wherein based on the at least one characteristic determined for the first memory portion a disturbance for the second memory portion is adjusted. ### Claim 21 (depends on 20) The integrated circuit according to claim 20, wherein the operation comprises at least one of: a read operation; a write operation; and an erase operation. ### Claim 22 (depends on 20) The integrated circuit according to claim 20, wherein the controller is configured to adjust the disturbance for the second memory portion by adjusting a disturb signal for the second memory portion. ### Claim 23 (depends on 22) The integrated circuit according to claim 22, wherein the controller is configured to adjust the disturb signal via a disturb voltage applied between a control gate and a well of the second memory portion. ### Claim 24 (depends on 22) The integrated circuit according to claim 22, wherein the controller is configured to adjust the disturb signal such that: for a first characteristic indicating that the first memory portion is rarely changed, an operation is conducted with a low disturb voltage; and for a second characteristic indicating that the first memory portion is frequently changed, the operation is conducted with a high disturb voltage. ### Claim 25 (depends on 22) The integrated circuit according to claim 22, wherein the controller is configured to adjust the disturb signal dependent on a number of access cycles already conducted for the first memory portion. ### Claim 26 (depends on 22) The integrated circuit according to claim 22, wherein the controller is configured to determine a success of a previous operation via a read operation and to adjust the disturb signal based on this success. ### Claim 27 (depends on 20) The integrated circuit according to claim 20, wherein the first memory portion and the second memory portion are each organized in blocks or pages. ### Claim 28 (depends on 20) The integrated circuit according to claim 20, wherein the first memory portion and the second memory portion each comprise at least one non-volatile memory selected from the following group: EEPROM; floating gate NVM; PCRAM; CBRAM; nano-crystal NVM; MONOS; and TANOS. ### Claim 29 A system for operating an integrated circuit, comprising: means for determining at least one characteristic of a first memory portion; and means for conducting an operation for the first memory portion, wherein based on the at least one characteristic determined a disturbance for a second memory portion is adjusted. ### Claim 30 (depends on 29) The system according to claim 29, wherein the operation comprises at least one of: a read operation; a write operation; and an erase operation. ### Claim 31 (depends on 29) The system according to claim 29, wherein the first memory portion and the second memory portion are parts of a single non-volatile memory. ### Claim 32 A method for conducting an operation for a first memory portion, the method comprising: determining at least one characteristic of the first portion of memory; and conducting the operation for the first portion of memory, wherein based on the at least one characteristic determined a disturbance for a second portion of memory is adjusted. ### Claim 33 (depends on 32) The method according to claim 32, wherein the operation comprises at least one of: a read operation; a write operation; and an erase operation. ### Claim 34 (depends on 32) The method of claim 32, wherein the first portion of memory and the second portion of memory are located on a non-volatile memory. ### Claim 35 (depends on 32) The method of claim 32, wherein the first portion of memory and the second portion of memory are coupled via a well of a non-volatile memory.