# US 2014/0153346 A1 · Read Assist Scheme for Reducing Read Access Time in a Memory

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- Number: US 2014/0153346 A1
- Document ID: US20140153346A1
- Status: Published application
- Kind: A1
- Application number: 13/706,276
- Filed: 2012-12-05
- Published: 2014-06-05
- Earliest claimed: 2012-12-05
- Assignees: LSI Corporation
- Applicants: Lsi Corporation
- Inventors: Uddip Roy; Vinod Rachamadugu; Vamsi Krishna Grandhi; Setti Shanmukheswara Rao
- Web page: https://patentgrep.com/patent/US20140153346A1

## CPC

- G11C 7/12: Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
- G11C 11/419: Read-write [R-W] circuits
- G11C 7/1048: {Data bus control circuits, e.g. precharging, presetting, equalising}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A read circuit includes a precharge circuit, coupled with at least a subset of bit lines and a sense circuit in a memory, and a transmission gate. The precharge circuit receives a first control signal and is operative during a first mode to set the bit lines to a first voltage level and to set an input to the sense circuit to a second voltage level. The transmission gate connects a given one of the bit lines with the sense circuit during a second mode as a function of a second control signal, such that when reading a first logic level from the selected memory cell, when the input of the sense circuit is connected with the given bit line, the given bit line is discharged to at least a third voltage, which is between the first and second voltage levels, thereby reducing a read access time in the memory.

## Claims

### Claim 1

A read circuit for use in a memory including a plurality of memory cells, at least one word line and a plurality of bit lines coupled with the memory cells for selectively accessing the memory cells, and at least one sense circuit for reading data stored in a selected one of the memory cells, the read circuit comprising:
a precharge circuit coupled with at least a subset of the bit lines and the sense circuit, the precharge circuit being operative to receive at least a first control signal, and being operative during a first mode to set the bit lines to a first voltage level and to set an input to the sense circuit to a second voltage level; and
a transmission gate operative to selectively connect a given one of the bit lines with the sense circuit during a second mode as a function of at least a second control signal, the second control signal being a delayed version of the first control signal, such that when reading a first logic level from the selected one of the memory cells, when the input of the sense circuit is connected with the given one of the bit lines, the given one of the bit lines has discharged to at least a third voltage, the third voltage being between the first and second voltage levels, thereby reducing a read access time in the memory.

### Claim 2 (depends on 1)

The read circuit of claim 1, further comprising a delay circuit operative to receive the first control signal and to generate the second control signal which is delayed from the first control signal by a prescribed delay, the prescribed delay being configured such that when reading the first logic level from the selected one of the memory cells, activation of the transmission gate is delayed until the given one of the bit lines has discharged to at least the third voltage.

### Claim 3 (depends on 2)

The read circuit of claim 2, wherein the delay circuit comprises a plurality of inverters connected together to form a delay chain, the prescribed delay associated with the delay circuit being a function of at least one of a number of inverters in the delay chain and a strength of one or more of the inverters in the delay chain.

### Claim 4 (depends on 2)

The read circuit of claim 2, wherein a value of the prescribed delay is configured so that a relationship between activation of the transmission gate relative to discharging of the given one of the bit lines is controlled to ensure that the read access time of the memory is not determined by a time to read the first logic level.

### Claim 5 (depends on 1)

The read circuit of claim 1, wherein the third voltage is about halfway between the first and second voltage levels.

### Claim 6 (depends on 1)

The read circuit of claim 1, wherein the third voltage is set to a level whereby a charge developed on the input of the sense circuit when reading the first logic level from the selected one of the memory cells does not switch a logic state of an output signal generated by the read circuit.

### Claim 7 (depends on 1)

The read circuit of claim 1, further comprising a feedback circuit coupled with at least the given one of the bit lines, the feedback circuit being operative, when reading a second logic level from the selected one of the memory cells, to establish a conducting path to hold the given one of the bit lines at the first voltage level.

### Claim 8 (depends on 7)

The read circuit of claim 7, wherein the first logic level is indicative of a logic “0” and the second logic level is indicative of a logic “1.”

### Claim 9 (depends on 1)

The read circuit of claim 1, wherein the first mode is a precharge mode and the second mode is a read mode.

### Claim 10 (depends on 1)

The read circuit of claim 1, wherein the precharge circuit comprises an NFET device having a first source/drain connected with the input to the sense circuit, a second source/drain configured for connection with a voltage source at the second voltage level, and a gate configured to receive the first control signal.

### Claim 11 (depends on 1)

The read circuit of claim 1, wherein a discharge rate of the given one of the bit lines is controlled as a function of a drive strength of at least one of a pass gate and a pull-down transistor in the selected one of the memory cells in the memory.

### Claim 12 (depends on 1)

The read circuit of claim 1, wherein a voltage developed on the input of the sense circuit substantially linearly tracks a voltage developed on the given one of the bit lines, thereby reducing a delay through the transmission gate.

### Claim 13 (depends on 1)

The read circuit of claim 1, wherein at least a portion of the read circuit is fabricated in at least one integrated circuit.

### Claim 14

A memory circuit, comprising:
a plurality of memory cells;
at least one word line and a plurality of bit lines, the word line and bit lines being coupled with the memory cells for selectively accessing the memory cells;
at least one sense circuit operative to read data stored in a selected one of the memory cells;
a controller operative to receive, as input control signals, an address signal and a data signal, and to generate a plurality of output control signals for accessing one or more of the plurality of memory cells as a function of the input control signals; and
a read circuit, the read circuit comprising:
a precharge circuit coupled with at least a subset of the bit lines and the sense circuit, the precharge circuit being operative to receive at least a first control signal, and being operative during a first mode to set the bit lines to a first voltage level and to set an input to the sense circuit to a second voltage level; and
a transmission gate operative to selectively connect a given one of the bit lines with the sense circuit during a second mode as a function of at least a second control signal, the second control signal being a delayed version of the first control signal, such that when reading a first logic level from the selected one of the memory cells, when the input of the sense circuit is connected with the given one of the bit lines, the given one of the bit lines is discharged to at least a third voltage, the third voltage being between the first and second voltage levels, thereby reducing a read access time in the memory circuit.

### Claim 15 (depends on 14)

The memory circuit of claim 14, wherein the read circuit further comprises a delay circuit operative to receive the first control signal and to generate the second control signal which is delayed from the first control signal by a prescribed delay, the prescribed delay being configured such that when reading the first logic level from the selected one of the memory cells, activation of the transmission gate is delayed until the given one of the bit lines has discharged to at least the third voltage.

### Claim 16 (depends on 15)

The memory circuit of claim 15, wherein the delay circuit comprises a plurality of inverters connected together to form a delay chain, the prescribed delay associated with the delay circuit being a function of at least one of a number of inverters in the delay chain and a strength of one or more of the inverters in the delay chain.

### Claim 17 (depends on 15)

The memory circuit of claim 15, wherein a value of the prescribed delay is configured so that activation of the transmission gate relative to discharging of the given one of the bit lines is controlled to ensure that the read access time of the memory circuit is not determined by a time to read the first logic level.

### Claim 18 (depends on 14)

The memory circuit of claim 14, wherein the third voltage is set to a level whereby a charge developed on the input of the sense circuit when reading the first logic level from the selected one of the memory cells does not switch a logic state of an output signal generated by the read circuit.

### Claim 19 (depends on 14)

The memory circuit of claim 14, further comprising a feedback circuit coupled with at least the given one of the bit lines, the feedback circuit being operative, when reading a second logic level from the selected one of the memory cells, to establish a conducting path to hold the given one of the bit lines at the first voltage level.

### Claim 20 (depends on 14)

The memory circuit of claim 14, wherein a discharge rate of the given one of the bit lines is controlled as a function of a drive strength of at least one of a pass gate and a pull-down transistor in the selected one of the memory cells in the memory circuit.

### Claim 21 (depends on 14)

The memory circuit of claim 14, wherein a voltage developed on the input of the sense circuit substantially linearly tracks a voltage developed on the given one of the bit lines, thereby reducing a delay through the transmission gate.

### Claim 22 (depends on 14)

The memory circuit of claim 14, wherein at least a portion of the memory circuit is fabricated in at least one integrated circuit.