# US 2014/0153344 A1 · Semiconductor memory device, system having the same and method for generating reference voltage for operating the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0153344 A1 - Document ID: US20140153344A1 - Status: Published application - Kind: A1 - Application number: 14/010,680 - Filed: 2013-08-27 - Published: 2014-06-05 - Earliest claimed: 2012-12-04 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Dong Kyun KIM - Web page: https://patentgrep.com/patent/US20140153344A1 ## CPC - G11C 5/147: {Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence)} - G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits - G11C 2207/2254: Calibration - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A semiconductor memory device and a method for generating a reference voltage needed for operating the same are disclosed. The semiconductor memory device includes a first decoder configured to generate a default set signal in response to a reset signal and a clock enable signal, a second decoder configured to generate a reference voltage set signal in response, and a reference voltage provider configured to generate an internal reference voltage. ## Claims ### Claim 1 A semiconductor memory device comprising: a first decoder configured to generate a default set signal based on a reset signal and a clock enable signal; a second decoder configured to generate a reference voltage set signal based on the default set signal; and a reference voltage provider configured to generate an internal reference voltage based on the reference voltage set signal. ### Claim 2 (depends on 1) The semiconductor memory device according to claim 1, wherein the first decoder generates the default set signal according to a logic state of the clock enable signal at a transition time point of the reset signal. ### Claim 3 (depends on 2) The semiconductor memory device according to claim 2, wherein the default set signal is generated in such a manner that a magnitude of the internal reference voltage has a predetermined ratio with respect to a driving voltage of the reference voltage provider. ### Claim 4 (depends on 3) The semiconductor memory device according to claim 3, wherein: the first decoder, if the clock enable signal has a first logic state at a transition time point of the reset signal, generates a first default set signal in a manner that a ratio of the internal reference voltage to the driving voltage has a first value; and the first decoder, if the clock enable signal has a second logic state at a transition time point of the reset signal, generates a second default set signal in a manner that a ratio of the internal reference voltage to the driving voltage has a second value. ### Claim 5 (depends on 1) The semiconductor memory device according to claim 1, wherein the reference voltage provider is driven in response to at least one of a core power-supply voltage and an input/output power-supply voltage. ### Claim 6 (depends on 5) The semiconductor memory device according to claim 5, wherein the reference voltage provider is driven by the core power-supply voltage, and the internal reference voltage is a command/address-buffer reference voltage. ### Claim 7 (depends on 5) The semiconductor memory device according to claim 5, wherein the reference voltage provider is driven by the input/output power-supply voltage, and the internal reference voltage is a data-buffer reference voltage. ### Claim 8 (depends on 1) The semiconductor memory device according to claim 1, wherein the reference voltage provider includes a voltage divider. ### Claim 9 (depends on 1) The semiconductor memory device according to claim 1, further comprising: a register configured to generate a command/address set signal in response to a command/address input, and provide the command/address set signal to the second decoder. ### Claim 10 (depends on 9) The semiconductor memory device according to claim 9, wherein: after the internal reference voltage is set up during the power-up process, the internal reference voltage is trained in response to the command/address set signal. ### Claim 11 A method for generating a reference voltage, comprising: generating a default set signal based on a reset signal and a clock enable signal; generating a reference voltage set signal in response to the default set signal; and generating an internal reference voltage in response to the reference voltage set signal and a driving voltage. ### Claim 12 (depends on 11) The method according to claim 11, wherein the internal reference voltage comprises a command/address-buffer reference voltage and a data-buffer reference voltage. ### Claim 13 (depends on 12) The method according to claim 12, further comprising: after setting up at least one of the command/address-buffer reference voltage and the data-buffer reference voltage during the power-up process, training at least one of the command/address-buffer reference voltage and the data-buffer reference voltage in response to the driving voltage and a command/address input. ### Claim 14 (depends on 13) The method according to claim 13, wherein generating the reference voltage set signal based on the default set signal includes: generating the reference voltage set signal in response to the command/address input, after setting up the reference voltage. ### Claim 15 (depends on 12) The method according to claim 12, wherein generating the internal reference voltage in response to the reference voltage set signal and the driving voltage includes: generating the command/address-buffer reference voltage if the driving voltage corresponds to a core power-supply voltage; and generating the data-buffer reference voltage if the driving voltage corresponds to an input/output power-supply voltage. ### Claim 16 (depends on 12) The method according to claim 12, wherein generating the default set signal in response to the reset signal and the clock enable signal during the power-up process includes: generating the default set signal according to a logic state of the clock enable signal at a rising edge of the reset signal. ### Claim 17 A memory system, comprising: a semiconductor memory device; a memory controller configured to control the memory device; a memory interface configured to communicate between the semiconductor memory device and the memory controller; and a microprocessor configured to control the memory controller; wherein the semiconductor memory device comprises: a first decoder configured to generate a default set signal based on a reset signal and a clock enable signal; a second decoder configured to generate a reference voltage set signal based on the default set signal; and a reference voltage provider configured to generate an internal reference voltage based on the reference voltage set signal. ### Claim 18 (depends on 17) The memory system according to claim 17, wherein the first decoder generates the default set signal according to a logic state of the clock enable signal at a transition time point of the reset signal. ### Claim 19 (depends on 18) The memory system according to claim 18, wherein the default set signal is generated in such a manner that a magnitude of the internal reference voltage has a predetermined ratio with respect to a driving voltage of the reference voltage provider. ### Claim 20 (depends on 17) The memory system according to claim 17, wherein the reference voltage provider generates a command/address-buffer reference voltage or a data-buffer reference voltage in response to a driving voltage.