# US 2014/0153342 A1 · Semiconductor integrated circuit and method for monitoring reference voltage thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0153342 A1 - Document ID: US20140153342A1 - Status: Published application - Kind: A1 - Application number: 13/845,909 - Filed: 2013-03-18 - Published: 2014-06-05 - Earliest claimed: 2012-12-03 - Assignees: SK hynix Inc. - Applicants: SK Hynix Inc. - Inventors: Se Jin YOO - Web page: https://patentgrep.com/patent/US20140153342A1 ## CPC - G11C 7/1096: {Write circuits, e.g. I/O line write drivers} - G11C 7/1048: {Data bus control circuits, e.g. precharging, presetting, equalising} - G11C 7/1066: {Output synchronization} - G11C 7/1069: {I/O lines read out arrangements} - G11C 7/1084: {Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load} - G11C 7/14: Dummy cell management; Sense reference voltage generators - G11C 29/021: {in voltage or current generators} - G11C 29/1201: {comprising I/O circuitry} - G11C 29/48: Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths - G11C 2029/0409: {Online test} - G11C 2207/105: Aspects related to pads, pins or terminals - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A semiconductor integrated circuit includes a write path coupled to a pad, a read path coupled to the pad, and a reference voltage output control block configured to apply a reference voltage to the pad through the write path in response to a reference voltage monitoring signal. The read path is electrically isolated from the pad in response to the reference voltage monitoring signal. ## Claims ### Claim 1 A semiconductor integrated circuit comprising: a write path electrically coupled to a pad; a read path electrically coupled to the pad; and a reference voltage output control block configured to apply a reference voltage to the pad through the write path in response to a reference voltage monitoring signal, wherein the read path is electrically isolated from the pad in response to the reference voltage monitoring signal. ### Claim 2 (depends on 1) The semiconductor integrated circuit according to claim 1, wherein the write path comprises: an input buffer coupled to the pad. ### Claim 3 (depends on 2) The semiconductor integrated circuit according to claim 2, wherein the reference voltage output control block is configured to apply the reference voltage to a path between the pad and the input buffer. ### Claim 4 (depends on 1) The semiconductor integrated circuit according to claim 1, wherein the read path comprises: an output driver configured to electrically disconnect an output terminal of the output driver from the pad in response to the reference voltage monitoring signal. ### Claim 5 (depends on 1) The semiconductor integrated circuit according to claim 1, wherein the output driver is configured to drive a signal to be transmitted to the pad in response to a termination signal and data. ### Claim 6 (depends on 5) The semiconductor integrated circuit according to claim 5, wherein the read path further comprises: a data output unit configured to output the data to the output driver in response to a clock signal and the termination signal. ### Claim 7 (depends on 5) The semiconductor integrated circuit according to claim 5, wherein the termination signal is provided from a controller outside the semiconductor integrated circuit. ### Claim 8 A semiconductor integrated circuit comprising: a pad; a core block; an input buffer configured to receive external data through the pad; a peripheral circuit block configured to write the external data which is transmitted through the input buffer into the core block, or to receive data read from the core block; an output driver configured to receive the data read from the core block through the peripheral circuit block, and to output the data to the pad; and a reference voltage output control block configured to apply an internal reference voltage to the pad in response to a reference voltage monitoring signal, wherein the output driver is electrically isolated from the pad in response to the reference voltage monitoring signal. ### Claim 9 (depends on 8) The semiconductor integrated circuit according to claim 8, wherein the reference voltage output control block is configured to apply the reference voltage to a path between the pad and the input buffer. ### Claim 10 (depends on 8) The semiconductor integrated circuit according to claim 8, wherein the output driver is configured to drive a signal to be transmitted to the pad using a predetermined termination resistance value in response to a termination signal and data. ### Claim 11 (depends on 10) The semiconductor integrated circuit according to claim 10, wherein the output driver is configured to be electrically discoupled from the pad, regardless of the termination signal, when the reference voltage monitoring signal is activated. ### Claim 12 (depends on 8) The semiconductor integrated circuit according to claim 8, wherein the output driver comprises: a driving section configured to pull-up or pull-down a signal to be transmitted to the pad; and a driving control section configured to control the driving section in response to the reference voltage monitoring signal, a termination signal, and data. ### Claim 13 (depends on 12) The semiconductor integrated circuit according to claim 12, wherein the driving section comprises: a pull-up transistor array coupled to a power supply terminal; a termination resistor array coupled to the pull-up transistor array; and a pull-down transistor array coupled between the termination resistor array and a ground terminal. ### Claim 14 (depends on 10) The semiconductor integrated circuit according to claim 10, wherein the termination signal is provided from a controller outside the semiconductor integrated circuit. ### Claim 15 A method for monitoring a reference voltage of a semiconductor integrated circuit, comprising the steps of: entering a reference voltage monitoring mode; outputting a reference voltage to a predetermined pad through a write path of the semiconductor integrated circuit when entering the reference voltage monitoring mode; and electrically isolating a read path of the semiconductor integrated circuit from the pad when entering the reference voltage monitoring mode. ### Claim 16 (depends on 15) The method according to claim 15, wherein the step of isolating the read path from the pad includes: driving a signal to be transmitted to the pad, wherein the signal has a predetermined termination resistance value when a termination signal is activated. ### Claim 17 (depends on 16) The method according to claim 16, wherein the termination signal is an external signal provided from an exterior of the semiconductor integrated circuit. ### Claim 18 (depends on 16) The method according to claim 16, wherein the step of isolating the read path includes: deactivating the termination signal in the semiconductor integrated circuit. ### Claim 19 (depends on 16) The method according to claim 16, wherein the step of isolating the read path includes: deactivating the termination signal using a reference voltage monitoring signal used for entering the reference voltage monitoring mode. ### Claim 20 A semiconductor integrated circuit comprising: a pad; an input buffer configured to receive a write data from the pad and electrically coupled to the pad; an output driver configured to transmit a read data to the pad and selectively coupled to the pad in response to a reference voltage monitoring signal.