# US 2014/0153337 A1 · Semiconductor memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0153337 A1 - Document ID: US20140153337A1 - Status: Published application - Kind: A1 - Application number: 14/174,538 - Filed: 2014-02-06 - Published: 2014-06-05 - Earliest claimed: 2011-09-07 - Assignees: Kabushiki Kaisha Toshiba - Applicants: Kabushiki Kaisha Toshiba - Inventors: Hiroshi MAEJIMA - Web page: https://patentgrep.com/patent/US20140153337A1 ## CPC - G11C 16/10: Programming or data input circuits - G11C 11/5621: {using charge storage in a floating gate} - G11C 16/04: using variable threshold transistors, e.g. FAMOS - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/3427: {Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written} - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - G11C 11/5628: {Programming or writing circuits; Data input circuits} - G11C 16/107: {Programming all cells in an array, sector or block to the same state prior to flash erasing} - G11C 2213/75: Array having a NAND structure comprising, for example, memory cells in series or memory elements in series, a memory element being a memory cell in parallel with an access transistor - G11C: STATIC STORES (semiconductor memory devices H10B) - H10B: ELECTRONIC MEMORY DEVICES ## Abstract According to one embodiment, a semiconductor memory device includes memory cells, word lines, a driver circuit, and a control circuit. The memory cells are stacked above a semiconductor substrate, and each includes a charge accumulation layer and control gate. The word lines are coupled to the control gates. The driver circuit repeats a programming operation to write data in a memory cell coupled to a selected word line. In the programming operation, a first voltage is applied to the selected word line, a second voltage to a first unselected word line, and a third voltage to a second unselected word line. The control circuit steps up the first voltage and steps down the second voltage in repeating the programming. ## Claims ### Claim 1 A semiconductor memory device comprising: a plurality of memory cells including current paths coupled in series, and each including a charge accumulation layer and a control gate, the plurality of memory cells being stacked above a semiconductor substrate; a plurality of word lines coupled to the control gates; a driver circuit configured to repeat a programming operation to write data in a memory cell coupled to a selected word line, wherein a first voltage is applied to the selected word line, a second voltage is applied to a first unselected word line, and a third voltage is applied to a second unselected word line, in the programming operation; and a control circuit configured to step up the first voltage and step down the second voltage in repeating the programming operation. ### Claim 2 (depends on 1) The device according to claim 1, wherein the first unselected word line is adjacent to the selected word line. ### Claim 3 (depends on 2) The device according to claim 2, wherein the control circuit steps down the second voltage after the number of times of repetition of the programming operation has reached a first count. ### Claim 4 (depends on 2) The device according to claim 2, wherein the control circuit holds the second voltage constant after the number of times of repetition of the programming operation has reached a second count. ### Claim 5 (depends on 2) The device according to claim 2, wherein the memory cell is configured to hold data having not less than four levels in accordance with a threshold voltage, and the second voltage is stepped down when writing a level having a highest threshold voltage among the not less than four levels. ### Claim 6 (depends on 2) The device according to claim 2, wherein the control circuit steps down the second voltage after the first voltage has reached a first threshold value. ### Claim 7 (depends on 2) The device according to claim 2, wherein the control circuit holds the second voltage constant after the first voltage has reached a second threshold value. ### Claim 8 (depends on 2) The device according to claim 2, wherein the control circuit holds the third voltage constant in repeating the programming operation. ### Claim 9 (depends on 2) The device according to claim 2, wherein the control circuit steps up the third voltage in repeating the programming operation. ### Claim 10 (depends on 2) The device according to claim 2, wherein the second voltage and the third voltage turn on the memory cell, and the first voltage is higher than the second voltage and the third voltage. ### Claim 11 A data write method of a semiconductor memory device including a plurality of memory cells including current paths coupled in series, and stacked above a semiconductor substrate, comprising: programming data in a selected memory cell by applying a first voltage to a gate of the selected memory cell, a second voltage to a gate of a first unselected memory cell, and a third voltage to a gate of a second unselected memory cell; and repeating the programming while stepping up the first voltage and stepping down the second voltage. ### Claim 12 (depends on 11) The method according to claim 11, wherein the first unselected memory cell is adjacent to the selected memory cell. ### Claim 13 (depends on 12) The method according to claim 12, wherein the second voltage is stepped down after the number of times of repetition of the programming has reached a first count. ### Claim 14 (depends on 12) The method according to claim 12, wherein the second voltage is held constant after the number of times of repetition of the programming has reached a second count. ### Claim 15 (depends on 12) The method according to claim 12, wherein the memory cell is configured to hold data having not less than four levels in accordance with a threshold voltage, and the second voltage is stepped down when writing a level having a highest threshold voltage among the not less than four levels. ### Claim 16 (depends on 12) The method according to claim 12, wherein the second voltage is stepped down after the first voltage has reached a first threshold value. ### Claim 17 (depends on 12) The method according to claim 12, wherein the second voltage is held constant after the first voltage has reached a second threshold value. ### Claim 18 (depends on 12) The method according to claim 12, wherein the third voltage is held constant in repeating the programming. ### Claim 19 (depends on 12) The method according to claim 12, wherein the third voltage is stepped up whenever the programming is repeated. ### Claim 20 (depends on 12) The method according to claim 12, wherein the second voltage and the third voltage turn on the memory cell, and the first voltage is higher than the second voltage and the third voltage.