# US 2014/0153335 A1 · Asynchronous/synchronous interface

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- Number: US 2014/0153335 A1
- Document ID: US20140153335A1
- Status: Published application
- Kind: A1
- Application number: 14/063,773
- Filed: 2013-10-25
- Published: 2014-06-05
- Earliest claimed: 2008-06-02
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Dean K. Nobunaga; June Lee; Chih Liang Chen
- Web page: https://patentgrep.com/patent/US20140153335A1

## CPC

- G11C 7/1072: {for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories}
- G06F 13/1694: {Configuration of memory controller to different memory types}
- G11C 7/10: Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C 7/1045: {Read-write mode select circuits}
- G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C 14/0009: {in which the volatile element is a DRAM cell}
- G11C 16/10: Programming or data input circuits
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode.

## Claims

### Claim at position 1

1-20. (canceled)

### Claim 21

A memory system comprising:
a memory access device;
a memory device coupled to the memory access device, the memory device comprising:
a memory cell array; and
a memory interface coupled to the memory cell array and configured for switchably operating in either an asynchronous mode or a synchronous mode,
wherein three or fewer additional memory interface control signals are utilized in the synchronous mode in addition to memory interface control signals utilized in the asynchronous mode.

### Claim 22 (depends on 21)

The memory system of claim 21, wherein the three or fewer additional memory interface signals at least includes two signals complementary to memory interface control signals utilized in the synchronous mode.

### Claim 23 (depends on 21)

The memory system of claim 21, wherein the three or fewer additional memory interface control signals includes a bidirectional data strobe signal.

### Claim 24 (depends on 23)

The memory system of claim 23, wherein the memory interface is configured to utilize a signal on a first contact of the memory interface as a write enable signal in an asynchronous mode and as a clock signal in a synchronous mode, and the memory interface is configured to utilize a signal on a second contact of the memory interface as a read enable signal in the asynchronous mode and as a write/read signal in the synchronous mode.

### Claim 25 (depends on 21)

The memory system of claim 21, wherein the three or fewer additional memory interface control signals include a bidirectional data strobe signal and a signal complementary to a memory interface control signal utilized in the synchronous mode.

### Claim 26 (depends on 21)

The memory system of claim 21, wherein the three or fewer additional memory interface control signals include a bidirectional data strobe signal, a complementary clock signal, and a complementary bidirectional data strobe signal.

### Claim 27

A memory system comprising:
a memory access device;
a memory device coupled to the memory access device, the memory device comprising:
a memory cell array; and
a memory interface coupled to the memory cell array and configured for switchably operating in either an asynchronous mode or a synchronous mode,
wherein the memory interface includes three or fewer additional memory interface contacts in addition to memory interface contacts utilized in the asynchronous mode.

### Claim 28 (depends on 27)

The memory system of claim 27, wherein the three or fewer additional memory interface contacts includes only one additional memory interface contact in addition to the memory interface contacts utilized in the asynchronous mode.

### Claim 29 (depends on 28)

The memory system of claim 28, wherein the memory interface is configured to utilize a signal on the one additional memory interface contact as a bidirectional data strobe signal in the synchronous mode.

### Claim 30 (depends on 27)

The memory system of claim 27, wherein the memory interface is configured to utilize a signal on the three or fewer additional memory interface contacts as a bidirectional data strobe signal, a complimentary bidirectional data strobe signal, and/or a complimentary clock signal.

### Claim 31 (depends on 30)

The memory system of claim 30, wherein the memory interface is configured to utilize a signal on a first memory interface contact as a write enable signal in the asynchronous mode and as a clock signal in the synchronous mode, and to utilize a signal on a second memory interface contact of the memory interface contacts as a read enable signal in the asynchronous mode and as a write/read signal in the synchronous mode.

### Claim 32

A memory system comprising:
a memory access device;
a memory device coupled to the memory access device, the memory device comprising:
a memory cell array; and
a memory interface configured for switchably operating in either an asynchronous mode or a synchronous mode,
wherein an additional memory interface contact for a bi-directional data strobe signal is utilized in the synchronous mode in addition to memory interface contacts utilized in the asynchronous mode.

### Claim 33 (depends on 32)

The memory system of claim 32, wherein the memory interface is configured to utilize a signal on a first memory interface contact of the memory interface contacts as a write enable signal in the asynchronous mode and as a clock signal in the synchronous mode, and to utilize a signal on a second memory interface contact of the memory interface contacts as a read enable signal in the asynchronous mode and as a write/read signal in the synchronous mode.

### Claim 34 (depends on 32)

The memory system of claim 32, wherein the memory interface is configured to power-up in the asynchronous mode, and switch to the synchronous mode responsive to detecting a clock signal.

### Claim 35 (depends on 32)

The memory system of claim 32, wherein the memory interface is configured to power-up in the asynchronous mode, and switch to the synchronous mode responsive to detecting a clock signal on one of the memory interface contacts utilized in the asynchronous mode.

### Claim 36 (depends on 32)

The memory system of claim 32, wherein the memory interface is configured to switch operation of the memory interface to the synchronous mode responsive to receiving a SET Feature command while operating in the asynchronous mode.

### Claim 37 (depends on 32)

The memory system of claim 32, wherein the memory interface is configured to switch operation of the memory interface to the asynchronous mode responsive to receiving a SET Feature command while operating in the synchronous mode.

### Claim 38 (depends on 32)

The memory system of claim 32, wherein the asynchronous mode or the synchronous mode is selected using programmable elements of the memory device.

### Claim 39 (depends on 32)

The memory system of claim 32, wherein the memory interface is configured to switch between the asynchronous mode and the synchronous mode using a GET Feature command.

### Claim 40 (depends on 32)

The memory system of claim 32, wherein the additional memory interface contact for the bidirectional data strobe signal is the only additional memory interface contact that is utilized in the synchronous mode in addition to the memory interface contacts utilized in the asynchronous mode.