# US 2014/0153334 A1 · Termination for complementary signals

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- Number: US 2014/0153334 A1
- Document ID: US20140153334A1
- Status: Published application
- Kind: A1
- Application number: 14/174,555
- Filed: 2014-02-06
- Published: 2014-06-05
- Earliest claimed: 2011-11-22
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: William Kammerer; Kalyan Kavalipurapu
- Web page: https://patentgrep.com/patent/US20140153334A1

## CPC

- H03K 19/018514: {with at least one differential stage (H03K19/018528 and H03K19/018542 take precedence)}
- G11C 16/04: using variable threshold transistors, e.g. FAMOS
- H03K 19/0005: {Modifications of input or output impedance}
- H04L 25/0278: {Arrangements for impedance matching}
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

Apparatuses including termination for complementary signals are described, along with methods for terminating complementary signals. One such apparatus includes a termination transistor including a first node configured to receive a first complementary signal and a second node configured to receive a second complementary signal. A regulation circuit can generate a regulated voltage to render the termination transistor conductive with a substantially constant resistance. In one such method, a first complementary signal is received at a drain of a termination transistor and a second complementary signal is received at a source of the termination transistor. Energy of the complimentary signals can be absorbed when the termination transistor is rendered conductive. Additional embodiments are also described.

## Claims

### Claim 1

A memory device comprising:
an array of memory cells; and
an input/output circuit, coupled to the array of memory cells, comprising:
a plurality of termination transistors coupled in parallel between first and second nodes, the first and second nodes each coupled to receive a respective signal that are substantially complementary to each other;
a circuit to generate a regulated voltage; and
a plurality of switches, each of the plurality of switches coupled between the circuit and a gate of a respective one of the termination transistors to selectively provide the regulated voltage to the gate of the respective termination transistor to render the respective termination transistor conductive with a substantially constant resistance.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein the circuit comprises a voltage follower circuit.

### Claim 3 (depends on 2)

The memory device of claim 2, wherein the voltage follower circuit comprises an operational amplifier having a non-inverting input coupled to a supply voltage, an inverting input coupled to receive a feedback signal, the operational amplifier to output the regulated voltage.

### Claim 4 (depends on 3)

The memory device of claim 3, wherein the voltage follower circuit comprises a temperature dependent current source.

### Claim 5 (depends on 1)

The memory device of claim 1, wherein the plurality of switches comprises a plurality of transistors coupled between their respective source nodes and drain nodes.

### Claim 6 (depends on 5)

The memory device of claim 5, further comprising a control logic circuit coupled to the plurality of switches.

### Claim 7 (depends on 6)

The memory device of claim 6, wherein the control logic circuit is coupled between the circuit and the plurality of switches such that the control logic circuit and the plurality of switches selectively provide the regulated voltage to the gate of the respective termination transistor.

### Claim 8

A memory device comprising:
an array of memory cells; and
an input/output circuit coupled to the array of memory cells and configured to facilitate bi-directional communication with the array of memory cells, the input/output circuit comprising:
a termination transistor configured to receive a pair of signals that are complementary to each other; and
a voltage regulation circuit coupled to a gate of the termination transistor to maintain the termination transistor with a substantially constant resistance during changes in a temperature of the memory device, wherein the regulation circuit comprises:
an operational amplifier having an input coupled to a constant supply voltage, an input coupled to a temperature varying voltage source, and an output coupled to the termination transistor, the operational amplifier configured to generate a regulated voltage on the output; and
a temperature dependent current source coupled to the temperature varying voltage source and configured to draw a current to ground, from the output of the operational amplifier, that changes with a temperature of the memory device.

### Claim 9 (depends on 8)

The memory device of claim 8, wherein the voltage regulation circuit comprises a transistor in a voltage follower configuration coupled between the output and the inverting input of the operational amplifier, the matched transistor being matched to the termination transistor.

### Claim 10 (depends on 9)

The memory device of claim 9, wherein the temperature varying voltage source is a voltage divider circuit coupled between the transistor in the voltage follower configuration and a reference voltage.

### Claim 11 (depends on 10)

The memory device of claim 10, wherein a node between two resistances of the voltage divider circuit is coupled to the temperature dependent current source to generate the temperature varying voltage in response to a temperature of the memory device.

### Claim 12 (depends on 8)

The memory device of claim 8, further comprising a plurality of termination transistors in parallel with the termination transistor, each of the plurality of termination transistors having gates coupled to one of a plurality of switches configured to selectively control application of the regulated voltage to each of the gates of the plurality of termination transistors.

### Claim 13 (depends on 12)

The memory device of claim 12, wherein the plurality of termination transistors each have a drain node coupled to the drain node of the other termination transistors and a source node coupled to a source node of the other termination transistors.

### Claim 14

A system comprising:
a memory controller; and
a memory device coupled to the memory controller, the memory device comprising:
a termination transistor configured to receive complementary signals on each of drain and source nodes; and
a voltage follower circuit coupled to a gate of the termination transistor configured to maintain a regulated voltage during changes in a temperature of the memory device including the voltage follower circuit and/or a supply voltage received by the voltage follower circuit, wherein the voltage follower circuit further comprises
an operational amplifier having a non-inverting input coupled to a supply voltage, an inverting input coupled to receive a feedback signal and an output, the operational amplifier to generate the regulated voltage on the output;
a voltage divider circuit coupled between a voltage follower configured transistor, coupled to the output, and a reference voltage node, wherein a node of the voltage divider is coupled to the inverting input of the operational amplifier to generate the feedback signal.

### Claim 15 (depends on 14)

The system of claim 14, further comprising a plurality of transistor switches between the voltage follower circuit and the termination transistor.

### Claim 16 (depends on 15)

The system of claim 15, further comprising a control logic circuit to control each of the plurality of transistor switches in response to a temperature of the memory device.

### Claim 17 (depends on 14)

The system of claim 14, further including a temperature dependent current source coupled to the node of the voltage divider.

### Claim 18 (depends on 14)

The system of claim 14, wherein each termination transistor comprises:
a source and a drain formed in a semiconductor material, the semiconductor material being coupled to a reference voltage node; and
a gate formed over a gate dielectric, the gate dielectric being formed over the semiconductor material between the source and the drain.

### Claim 19 (depends on 14)

The system of claim 14, wherein the memory device is a NAND flash memory device.