# US 2014/0153331 A1 · Multi-level cell memory device and operating method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0153331 A1 - Document ID: US20140153331A1 - Status: Published application - Kind: A1 - Application number: 14/096,281 - Filed: 2013-12-04 - Published: 2014-06-05 - Earliest claimed: 2012-12-04 - Assignees: Samsung Electronics Co., Ltd. - Inventors: Joonsuc JANG; Sangyong YOON - Web page: https://patentgrep.com/patent/US20140153331A1 ## CPC - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 7/1039: {using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers} - G11C 11/5628: {Programming or writing circuits; Data input circuits} - G11C 11/5642: {Sensing or reading circuits; Data output circuits} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/102: {External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators} - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 43/35: with cell select transistors, e.g. NAND - G11C: STATIC STORES (semiconductor memory devices H10B) - H10B: ELECTRONIC MEMORY DEVICES ## Abstract According to an example embodiment of inventive concepts, an operating method of a non-volatile memory device includes: performing a first hard decision read operation that includes applying a first voltage if a selected word line of the non-volatile memory device; storing a result of the first hard decision read operation at a first latch of a page buffer in the non-volatile memory device; performing a second hard decision read operation that includes applying a second voltage to the selected word line, the second voltage being higher than the first voltage; and generating a first soft decision value using a result of the first hard decision read operation stored at the first latch. ## Claims ### Claim 1 A method of operating a non-volatile memory device, comprising: performing a first hard decision read operation that includes applying a first voltage to a selected word line of the non-volatile memory device; storing a result of the first hard decision read operation at a first latch of a page buffer in the non-volatile memory device; performing a second hard decision read operation that includes applying a second voltage to the selected word line, the second voltage being higher than the first voltage; and generating a first soft decision value using a result of the first hard decision read operation stored at the first latch. ### Claim 2 (depends on 1) The method of claim 1, wherein the first hard decision read operation is a coarse read operation. ### Claim 3 (depends on 1) The method of claim 1, wherein the second hard decision read operation is a fine read operation. ### Claim 4 (depends on 1) The method of claim 1, further comprising: forming a second soft decision value by performing a soft decision read operation that includes applying a third voltage to the selected word line, the third voltage being higher than the second voltage. ### Claim 5 (depends on 4) The method of claim 4, further comprising: generating soft decision data by performing a logical operation on the first and second soft decision values using the page buffer. ### Claim 6 (depends on 5) The method of claim 5, further comprising: performing an additional error bit correction operation using the soft decision data if an error bit correction operation on the result of the second hard decision read operation fails. ### Claim 7 (depends on 5) The method of claim 5, wherein the logical operation is an XNOR operation. ### Claim 8 (depends on 4) The method of claim 4, further comprising: selectively pre-charging bit lines connected to off-state cells of the non-volatile memory device, based on a result of the second hard decision read operation, at execution of the soft decision read operation, the off-state cells each having a threshold voltage higher than the second voltage. ### Claim 9 (depends on 4) The method of claim 4, further comprising: performing a third hard decision read operation using a fourth voltage that is higher than the third voltage; and selectively pre-charging bit lines connected to memory cells of the non-volatile memory device having a threshold voltage between the second and the fourth voltage, at execution of the soft decision read operation, if results of the second hard decision read operation and the third hard decision read operations are stored in the page buffer. ### Claim at position 10 -16. (canceled) ### Claim 17 A method of operating a non-volatile memory device, comprising: performing a first hard decision read operation that includes applying a first read voltage to a selected word line of the non-volatile memory device; storing a result of the first hard decision read operation at a first latch of a page buffer in the non-volatile memory device; performing a second hard decision read operation that includes generating hard decision data by applying a second read voltage to the selected word line, the second read voltage being higher than the first read voltage; generating a first soft decision value using a result of the first hard decision read operation stored at the first latch without applying a first soft decision read voltage to the selected word line; storing the first soft decision value at a second latch of the page buffer; generating a second soft decision value by applying a soft decision read voltage to the selected word line, the soft decision read voltage being higher than the second read voltage; storing the second soft decision value at a third latch of the page buffer; and generating soft decision data using the page buffer by performing a logical operation on the first soft decision value and the second soft decision value. ### Claim 18 (depends on 17) The method of claim 17, wherein the logical operation is an XNOR operation. ### Claim 19 (depends on 17) The method of claim 17, further comprising: performing an error correction operation using the hard decision data; and performing an additional error correction operation using the soft decision data if the error correction operation using the hard decision data fails. ### Claim 20 (depends on 17) The method of claim 17, wherein at execution of the applying the soft decision read voltage, selectively pre-charging bit lines connected to memory cells of the non-volatile device based on the result of the second hard decision read operation. ### Claim 21 (depends on 17) The method of claim 17, further comprising: performing a third hard decision read operation using a fourth voltage that is higher than the third voltage; and at execution of the applying the soft decision read voltage, selectively pre-charging bit lines connected to memory cells of the non-volatile memory device that each have a threshold voltage between the second and the fourth voltage if results of the second hard decision read operation and the third hard decision read operation are stored in the page buffer. ### Claim 22 An method of operating a non-volatile memory device including at least one cell string having memory cells arranged between a string select transistor and a ground select transistor in a direction perpendicular to a substrate, the method of operating comprising: performing a first hard decision read operation that includes applying a first voltage to a selected word line of the non-volatile memory device; storing a result of the first hard decision read operation at a first latch of a page buffer of the non-volatile memory device; performing a second hard decision read operation that includes applying a second voltage to the selected word line, the second voltage being higher than the first voltage; and generating a first soft decision value using a result of the first hard decision read operation stored at the first latch without applying a first soft decision read voltage to the selected word line. ### Claim 23 A method of operating a non-volatile memory device, comprising: performing a first read operation that includes applying a first voltage to a selected word line of the non-volatile memory device; storing a result of the first read operation at a first latch of a page buffer of the non-volatile memory device; performing a second read operation that includes applying a second voltage to the selected word line, the second voltage being higher than the first voltage; performing an error correction operation on a result of the second read operation; and performing an additional error correction operation using soft decision data if the error correction operation on the result of the second read operation fails, generating the soft decision data by, performing a third read operation that includes applying a third voltage to the selected word line, the third voltage being higher than the second voltage, storing a result of the third read operation in an other latch of the page buffer, and performing a logical operation using the result of the first read operation stored in the first latch and the result of the third read operation stored in the other latch. ### Claim 24 (depends on 23) The method of claim 23, wherein the logical operation is an XNOR operation. ### Claim 25 (depends on 23) The method of claim 23, wherein the first read operation is a coarse read operation, and the second read operation is a fine read operation. ### Claim 26 (depends on 23) The method of claim 23, further comprising: selectively pre-charging bit lines connected to memory cells of the non-volatile memory device, based on the result of the second read operation, at execution of the third read operation. ### Claim 27 (depends on 23) The method of claim 23, wherein the non-volatile memory device includes a plurality of a NAND strings arranged in rows and columns, each NAND strings includes a plurality of memory cells stacked vertically on each other between a ground selection transistor and a string selection transistor, the non-volatile memory device includes a plurality of bit lines, each one of the plurality of bit lines is connected to the plurality of NAND strings in a same column, the selected word line is one of a plurality of word lines in the non-volatile memory device, and each one of the plurality of word lines is connected to a corresponding one of the plurality of memory cells at a same height in the plurality of NAND strings in a same row.