# US 2014/0153329 A1 · Nonvolatile memory device comprising page buffer and operation method thereof

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- Number: US 2014/0153329 A1
- Document ID: US20140153329A1
- Status: Published application
- Kind: A1
- Application number: 14/077,606
- Filed: 2013-11-12
- Published: 2014-06-05
- Earliest claimed: 2012-12-05
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Dongku KANG; Dae Yeal LEE
- Web page: https://patentgrep.com/patent/US20140153329A1

## CPC

- G11C 16/3459: {Circuits or methods to verify correct programming of nonvolatile memory cells}
- G11C 7/1039: {using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers}
- G11C 11/56: using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C 16/06: Auxiliary circuits, e.g. for writing into memory
- G11C 16/10: Programming or data input circuits
- G11C 16/24: Bit-line control circuits
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C 16/3481: {Circuits or methods to verify correct programming of nonvolatile memory cells whilst programming is in progress, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate programming}
- G11C 17/06: using diode elements (G11C17/14 takes precedence)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A nonvolatile memory device is provided which includes a cell array including a plurality of memory cells; a page buffer unit including a plurality of page buffers and configured to sense whether programming of selected memory cells is completed, at a program verification operation; and a control logic configured to provide a set pulse for setting data latches of each of the page buffers to a program inhibit state according to the sensing result, wherein the control logic provides the set pulse to at least two different page buffers such that data latches of the at least two different page buffers are set.

## Claims

### Claim 1

A nonvolatile memory device, comprising:
a cell array including a plurality of memory cells;
a page buffer unit including a plurality of page buffers and configured to perform a program verification operation in order to sense whether programming of selected memory cells is completed; and
control logic configured to provide a set pulse for setting data latches of each of the plurality of page buffers to a program inhibit state according to a result of the program verification operation, the control logic providing the set pulse to at least two of the plurality of page buffers such that data latches of the at least two of the plurality of page buffers are set.

### Claim 2 (depends on 1)

The nonvolatile memory device of claim 1, wherein each of the plurality of page buffers comprises a sensing latch for latching data corresponding to the result of the program verification operation.

### Claim 3 (depends on 2)

The nonvolatile memory device of claim 2, wherein the control logic further provides a plurality of set pulses for setting data latches of the page buffers during a clock cycle.

### Claim 4 (depends on 1)

The nonvolatile memory device of claim 1, wherein each of the plurality of page buffers comprises:
a first data latch configured to store a first bit to be programmed at a corresponding memory cell; and
a second data latch configured to store a second bit to be programmed at the corresponding memory cell.

### Claim 5 (depends on 4)

The nonvolatile memory device of claim 4, wherein the set pulse is simultaneously provided as a first latch set signal for setting the first data latch of one of the plurality of page buffers and as a second latch set signal for setting the second data latch of an other one of the plurality of page buffers.

### Claim 6 (depends on 4)

The nonvolatile memory device of claim 4, wherein the first bit corresponds to a most significant bit (MSB) of multiple bits to be programmed at the corresponding memory cell and the second bit is an other one of the multiple bits.

### Claim 7 (depends on 4)

The nonvolatile memory device of claim 4, wherein the control logic is configured to provide a first pulse stream for setting the first data latches of the page buffers and a second pulse stream for setting the second data latches of the page buffers.

### Claim 8 (depends on 7)

The nonvolatile memory device of claim 7, wherein the first pulse stream is provided during a first clock cycle period and the second pulse stream is provided during a second clock cycle period, the second clock cycle period following the first clock cycle period.

### Claim at position 9

9-14. (canceled)

### Claim 15

A nonvolatile memory device, comprising:
a first page buffer including a first data latch;
a second page buffer including a second data latch; and
control logic configured to control the first page buffer and the second page buffer by applying a set pulse simultaneously to both the first page buffer and the second page buffer, and
the first page buffer is configured to store first data in the first data latch in response to the set pulse, and
the second page buffer is configured to store second data in the second data latch in response to the set pulse.

### Claim 16 (depends on 15)

The nonvolatile memory device of claim 15, wherein
the first page buffer includes a first sensing latch, and the first page buffer is configured to store the first data in the first data latch according to the first data stored in the first sensing latch; and
the second page buffer includes a second sensing latch, and the second page buffer is configured to store the second data in the second data latch according to the second data stored in the second sensing latch.

### Claim 17 (depends on 16)

The nonvolatile memory device of claim 16, wherein the first page buffer and the second page buffer are each configured to maintain a target state in response to the set pulse.

### Claim 18 (depends on 16)

The nonvolatile memory device of claim 16, wherein the control logic is further configured to set the first page buffer and the second page buffer to a program inhibit state if a result of a program verification operation indicates that a programming operation has been completed.

### Claim 19 (depends on 18)

The nonvolatile memory device of claim 18, wherein
the first sensing latch is configured to store the first data corresponding to the result of the program verification operation, and
the second sensing latch is configured to store the second data corresponding to the result of the program verification operation.

### Claim 20 (depends on 18)

The nonvolatile memory device of claim 18, wherein the first data latch is configured to store most significant bit (MSB) data of the first page buffer and the second data latch is configured to store least significant bit (LSB) data of the second page buffer.