# US 2014/0153328 A1 · Complementary soi lateral bipolar for sram in a cmos platform

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- Number: US 2014/0153328 A1
- Document ID: US20140153328A1
- Status: Published application
- Kind: A1
- Application number: 13/691,823
- Filed: 2012-12-02
- Published: 2014-06-05
- Earliest claimed: 2012-12-02
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Jin Cai; Leland Chang; Jeffrey W. Sleight
- Web page: https://patentgrep.com/patent/US20140153328A1

## CPC

- G11C 11/40: using transistors
- G11C 11/411: using bipolar transistors only
- H10D 84/0123: {Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

An example embodiment is a memory array. The memory array includes a SOI substrate and lateral bipolar junction transistors (BJTs) fabricated on the SOI substrate. The BJTs form first and second inverters cross coupled to form a memory cell. A read circuit outputs the binary state of the memory cell. A power supply is configured to supply a Vdd voltage to the read circuit and to supply a Vcc and a Vee voltage to the first set of lateral bipolar transistors and the second set of lateral bipolar transistors, wherein the Vee voltage is at least zero volts and the Vcc voltage is greater than the Vee voltage and is equal to or less than the Vdd voltage.

## Claims

### Claim 1

A memory array comprising:
a semiconductor-on-insulator (SOI) substrate;
a first set of lateral bipolar junction transistors (BJTs) fabricated on the SOI substrate, the first set of lateral BJTs forming a first inverter having a first output terminal configured to invert a first input signal at a first input terminal; and
a second set of lateral BJTs fabricated on the SOI substrate, the second set of lateral BJTs forming a second inverter having a second output terminal configured to invert a second input signal at a second input terminal, the second inverter is cross coupled to the first inverter such that the first input terminal is electrically coupled to the second output terminal and the second input terminal is electrically coupled to the first output terminal;
a read circuit configured to output the binary state of the second output terminal, the read circuit including (a) a high impedance read input electrically coupled to the second output terminal, (b) a read enable input electrically coupled to a read word line, and (c) a read output electrically coupled to a read bit line; and
a power supply configured to supply a Vdd voltage to the read circuit and to supply a Vcc and a Vee voltage to the first set of lateral BJTs and the second set of lateral BJTs, wherein the Vee voltage is at least zero volts and the Vcc voltage is greater than the Vee voltage and is equal to or less than the Vdd voltage.

### Claim 2 (depends on 1)

The memory array of claim 1, wherein the Vcc voltage is at least five times greater than the Vee voltage.

### Claim 3 (depends on 1)

The memory array of claim 1, wherein the first set of lateral BJTs and the second set of lateral BJTs each includes:
a lateral PNP BJT fabricated on the SOI substrate, the lateral PNP BJT including a PNP base, a PNP emitter, and a PNP collector; and
a lateral NPN BJT fabricated on the SOI substrate, the lateral NPN BJT including a NPN base, a NPN emitter, and a NPN collector.

### Claim 4 (depends on 1)

The memory array of claim 1, further comprising:
wherein the read circuit includes a first read field effect transistor (FET) and a second read FET electrically coupled in series circuit;
wherein the high impedance read input is a gate terminal of the first read FET;
wherein the read enable input is a gate terminal of the second read FET; and
wherein the read output is a source terminal of the second read FET.

### Claim 5 (depends on 4)

The memory array of claim 4, wherein the first and second read FETs are n-channel FETs.

### Claim 6 (depends on 4)

The memory array of claim 4, wherein the first and second read FETs are p-channel FETs.

### Claim 7 (depends on 1)

The memory array of claim 1, wherein the high impedance read input is at least one mega ohms.

### Claim 8 (depends on 1)

The memory array of claim 1, a write circuit electrically coupled to a write word line and configured to change the state of the binary states of the first inverter and the second inverter, the write word line being separate from the read word line.

### Claim 9 (depends on 8)

The memory array of claim 8, wherein the write circuit comprises:
a first access transistor controlling electrical impedance from the first inverter to a write bit line true; and
a second access transistor controlling electrical impedance from the second inverter to a write bit line complement.

### Claim 10 (depends on 9)

The memory array of claim 9, wherein the first and second access transistors are field effect transistors (FETs).

### Claim 11 (depends on 10)

The memory array of claim 10, wherein the first and second access transistors are n-channel FETs.

### Claim 12 (depends on 10)

The memory array of claim 10, wherein the first and second access transistors are p-channel FETs.

### Claim 13 (depends on 9)

The memory array of claim 9, wherein each of the first and second access transistors includes a gate terminal coupled to a word write line.

### Claim 14 (depends on 9)

The memory array of claim 9, wherein the first and second access transistors are configured to write data to the memory cell.

### Claim at position 15

15-20. (canceled)