# US 2014/0153322 A1 · SRAM Cell Comprising FinFETs

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- Number: US 2014/0153322 A1
- Document ID: US20140153322A1
- Status: Published application
- Kind: A1
- Application number: 13/691,373
- Filed: 2012-11-30
- Published: 2014-06-05
- Earliest claimed: 2012-11-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company,
- Inventors: Jhon-Jhy Liaw
- Web page: https://patentgrep.com/patent/US20140153322A1

## CPC

- G11C 11/412: using field-effect transistors only
- H10B 10/125: {the MOSFET being a thin film transistor [TFT]}
- H10D 84/834: {comprising FinFETs}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A Static Random Access Memory (SRAM) cell includes a first long boundary and a second long boundary parallel to a first direction, and a first short boundary and a second short boundary parallel to a second direction perpendicular to the first direction. The first and the second long boundaries are longer than, and form a rectangle with, the first and the second short boundaries. A CVss line carrying a VSS power supply voltage crosses the first long boundary and the second long boundary. The CVss line is parallel to the second direction. A bit-line and a bit-line bar are on opposite sides of the CVss line. The bit-line and the bit-line bar are configured to carry complementary bit-line signals.

## Claims

### Claim 1

A Static Random Access Memory (SRAM) cell comprising:
a first long boundary and a second long boundary parallel to a first direction;
a first short boundary and a second short boundary parallel to a second direction perpendicular to the first direction, wherein the first and the second long boundaries are longer than, and form a rectangle with, the first and the second short boundaries;
a CVss line carrying a VSS power supply voltage crossing the first long boundary and the second long boundary, wherein the CVss line is parallel to the second direction; and
a bit-line and a bit-line bar on opposite sides of the CVss line, wherein the bit-line and the bit-line bar are configured to carry complementary bit-line signals.

### Claim 2 (depends on 1)

The SRAM cell of claim 1, wherein the CVss line is wider than the bit-line and the bit-line bar.

### Claim 3 (depends on 1)

The SRAM cell of claim 1, wherein a ratio of a length of the first long boundary to a length of the first short boundary is greater than about 2.

### Claim 4 (depends on 1)

The SRAM cell of claim 1 further comprising:
a p-well region in a center region of the SRAM cell, wherein the CVss line overlaps the p-well region; and
a first and a second n-well region on opposite sides of the p-well region.

### Claim 5 (depends on 4)

The SRAM cell of claim 4 further comprising:
a first pull-up Fin Field-Effect Transistor (FinFET) and a second pull-up FinFET formed on the first and the second n-well regions, respectively;
a first pull-down FinFET and a second pull-down FinFET formed on the p-well region; and
a first and a second pass-gate FinFET formed on the first and the second n-well regions, respectively.

### Claim 6 (depends on 1)

The SRAM cell of claim 1 further comprising a word-line parallel to the first direction.

### Claim 7 (depends on 6)

The SRAM cell of claim 6 further comprising a first CVdd line and a second CVdd line parallel to the first direction and on opposite sides of the word-line, wherein the first CVdd line and the second CVdd line are configured to carry a positive power supply voltage.

### Claim 8 (depends on 6)

The SRAM cell of claim 6 further comprising a first CVdd line and a second CVdd line parallel to the second direction and on opposite sides of the CVss line, wherein the first CVdd line and the second CVdd line are configured to carry a positive power supply voltage.

### Claim 9 (depends on 8)

The SRAM cell of claim 8 further comprising an third CVdd line parallel to the first direction, wherein the third CVdd line is over, and connected to, the first CVdd line and the second CVdd line.

### Claim 10

A Static Random Access Memory (SRAM) cell comprising:
a p-well region;
a first and a second n-well region on opposite sides of the p-well region;
a CVss line carrying a VSS power supply voltage over the p-well region, wherein the CVss line is parallel to an interface between the p-well region and the first n-well region;
a first pull-up Fin Field-Effect Transistor (FinFET) and a second pull-up FinFET in the first n-well region and the second n-well region, respectively;
a first pull-down FinFET and a second pull-down FinFET in the p-well region; and
a first pass-gate FinFET and a second pass-gate FinFET in the first n-well region and the second n-well region, respectively.

### Claim 11 (depends on 10)

The SRAM cell of claim 10 further comprising a bit-line and a bit-line bar on opposite sides of the CVss line, wherein the bit-line and a bit-line bar are configured to carry complementary bit-line signals.

### Claim 12 (depends on 10)

The SRAM cell of claim 10 further comprising a long boundary and a short boundary, with the short boundary shorter than the long boundary, wherein the CVss line is parallel to the short boundary.

### Claim 13 (depends on 12)

The SRAM cell of claim 12, wherein a length of the long boundary to a length of the short boundary is greater than about 2.

### Claim 14 (depends on 10)

The SRAM cell of claim 10 further comprising:
a third pull-up FinFET comprising a gate connected to gates of the first pull-up FinFET and the first pull-down FinFET;
a third pass-gate FinFET cascaded with the third pull-up FinFET; and
a read word-line connected to a gate of the third pass-gate FinFET.

### Claim 15 (depends on 10)

The SRAM cell of claim 10 further comprising a third pass-gate FinFET and a fourth pass-gate FinFET, wherein the first pass-gate FinFET and the second pass-gate FinFET form a portion of a first port of the SRAM cell, and wherein the third pass-gate FinFET and the fourth pass-gate FinFET form a portion of a second port of the SRAM cell.

### Claim 16

A Static Random Access Memory (SRAM) cell comprising:
a p-well region;
a first n-well region and a second n-well region on opposite sides of the p-well region;
a long boundary and a short boundary, with the short boundary shorter than the long boundary;
a CVss line carrying a VSS power supply voltage overlapping the p-well region, wherein the CVss line is parallel to the short boundary;
a bit-line and a bit-line bar on opposite sides of the CVss line, wherein the bit-line and the bit-line bar are configured to carry complementary bit-line signals, and wherein the bit-line and the bit-line bar overlap the first n-well region and the second n-well region, respectively;
a first pull-up Fin Field-Effect Transistor (FinFET) and a second pull-up FinFET in the first n-well region and the second n-well region, respectively;
a first pull-down FinFET and a second pull-down FinFET in the p-well region; and
a first pass-gate FinFET and a second pass-gate FinFET in the first n-well region and the second n-well region, respectively.

### Claim 17 (depends on 16)

The SRAM cell of claim 16, wherein a length of the long boundary to a length of the short boundary is greater than about 2.

### Claim 18 (depends on 16)

The SRAM cell of claim 16 further comprising;
a word-line parallel to the long boundary; and
a first CVdd line and a second CVdd line parallel to the long boundary and on opposite sides of the word-line, wherein the first CVdd line and the second CVdd line are configured to carry a positive power supply voltage.

### Claim 19 (depends on 16)

The SRAM cell of claim 16 further comprising:
a word-line parallel to the long boundary; and
a first CVdd line and a second CVdd line parallel to the short boundary and on opposite sides of the CVss line, wherein the first CVdd line and the second CVdd line are configured to carry a positive power supply voltage.

### Claim 20 (depends on 19)

The SRAM cell of claim 19 further comprising an third CVdd line parallel to the long boundary, wherein the third CVdd line is over the first CVdd line and the second CVdd line, and wherein the third CVdd line is configured to carry the positive power supply voltage.