# US 2014/0153321 A1 · Methods and Apparatus for FinFET SRAM Arrays in Integrated Circuits

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- Number: US 2014/0153321 A1
- Document ID: US20140153321A1
- Status: Published application
- Kind: A1
- Application number: 14/177,521
- Filed: 2014-02-11
- Published: 2014-06-05
- Earliest claimed: 2011-12-06
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Jhon-Jhy Liaw
- Web page: https://patentgrep.com/patent/US20140153321A1

## CPC

- G11C 11/419: Read-write [R-W] circuits
- G11C 11/412: using field-effect transistors only
- G11C 11/413: Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 86/215: {comprising FinFETs}
- H10D 89/10: Integrated device layouts
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Methods and apparatus for providing single finFET and multiple finFET SRAM arrays on a single integrated circuit are provided. A first single port SRAM array of a plurality of first bit cells is described, each first bit cell having a y pitch Y1 and an X pitch X1, the ratio of X1 to Y1 being greater than or equal to 2, each bit cell further having single fin finFET transistors to form a 6T SRAM cell and a first voltage control circuit; and a second single port SRAM array of a plurality of second bit cells, each second bit cell having a y pitch Y2 and an X pitch X2, the ratio of X2 to Y2 being greater than or equal to 3, each of the plurality of second bit cells comprising a 6T SRAM cell wherein the ratio of X2 to X1 is greater than about 1.1.

## Claims

### Claim 1

A method, comprising:
providing a first single port SRAM array on an integrated circuit, the first single port SRAM array comprising a plurality of first size bit cells each comprising:
a cross coupled inverter pair for storing data on a storage node and a complementary storage node each inverter comprising a single fin finFET pull up and a single fin finFET pull down device; and
a pair of pass gates each coupled between a bit line and a complementary bit line and a respective one of the storage node and the complementary storage node, each of the pass gates comprising a single fin finFET device having a gate coupled to a word line;
outputting a first cell positive voltage supply CVdd to the first size bit cells from a first voltage control circuit;
providing a second single port SRAM array on the integrated circuit, the second single port SRAM array comprising a plurality of second size bit cells each comprising:
a cross coupled inverter pair for storing data on a storage node and a complementary storage node, each inverter comprising a single fin finFET pull up and a multiple fin finFET pull down device; and
a pair of pass gates each coupled between a bit line and a complementary bit line and a respective one of the storage node and the complementary storage node, each of the pass gates comprising a multiple fin finFET device having a gate coupled to a word line;
outputting a second cell positive voltage supply CVdd to the second size bit cells from a second voltage control circuit;
coupling the first voltage control circuit and the second voltage control circuit to a peripheral voltage Vdd; and
operating the first voltage control circuit to vary the first cell positive voltage supply CVdd during selected operations.

### Claim 2 (depends on 1)

The method of claim 1, further comprising operating the first voltage control circuit to reduce the first cell positive voltage supply CVdd to a voltage lower than the peripheral voltage Vdd during write operations.

### Claim 3 (depends on 1)

The method of claim 1, further comprising operating the first voltage control circuit to output a first cell positive voltage supply CVdd that is equal to or greater than the peripheral voltage Vdd during read operations.

### Claim 4 (depends on 1)

The method of claim 1, further comprising operating the first and second voltage control circuits to reduce the first cell positive voltage supply CVdd and the second cell positive voltage supply CVdd during standby operations.

### Claim 5 (depends on 1)

The method of claim 1, further comprising providing a third SRAM array, the third SRAM array comprising a plurality of third size bit cell, each of the third size bit cells comprising:
two cross coupled inverters coupled to store data at a storage node and a complementary storage node, each of the cross coupled inverters comprising a p-type single fin finFET pull up transistor coupled between a cell positive supply voltage CVdd and a respective one of the storage node and the complementary storage node, an n-type single fin finFET pull down transistor coupled between a respective one of the storage node and the complementary storage node and a first cell negative supply voltage CVss;
two write pass gates each comprising a single fin finFET transistor having a gate coupled to a word line and coupling a respective one of a write bit line and a complementary write bit line to the corresponding storage node and complementary storage node; and
a read port comprising a read pass gate and a read pull down transistor coupled in series between a read bit line and a second cell negative supply voltage CVss, each of the read pass gate and read pull down transistors comprising a multiple fin finFET device.

### Claim 6

A method comprising:
providing a first single port SRAM array on an integrated circuit, wherein the first single port SRAM array comprises a plurality of first bit cells arranged in rows and columns, each of the plurality of first bit cells having a y pitch of distance Y1 and an x pitch of distance X1, wherein a ratio of X1 to Y1 is greater than or equal to 2, and wherein each of the plurality of first bit cells forms a 6T SRAM cell of single fin finFET transistors;
providing a first cell positive voltage supply CVdd from a first voltage control circuit to each of the first bit cells;
providing a second single port SRAM array on the integrated circuit, wherein the second single port SRAM array comprises a plurality of second bit cells arranged in rows and columns, each of the plurality of second bit cells having a y pitch of distance Y2 and an x pitch of distance X2, wherein a ratio of X2 to Y2 is greater than or equal to 3, and wherein each of the plurality of second bit cells comprises a 6T SRAM cell including multiple fin finFET transistors; and
providing a second cell positive voltage supply CVdd from a second voltage control circuit to each of the second bit cells,
wherein a ratio of X2 to X1 is greater than about 1.1.

### Claim 7 (depends on 6)

The method of claim 6, the method further comprising connecting the first cell positive voltage supply CVdd to the first voltage control circuit, wherein:
each of the first bit cells further comprises:
two inverters cross coupled between a storage node and a complementary storage node, each of the two inverters comprising a single fin finFET pull up transistor coupled between the cell positive voltage supply CVdd and the corresponding one of the storage nodes and a single fin finFET pull down transistor coupled between the respective one of the storage nodes and a cell negative voltage supply CVss; and
a pair of pass gates coupled between a respective one of a bit line and a complementary bit line and a corresponding one of the storage node and the complementary storage node, each pass gate comprising a single fin finFET transistor with a gate terminal coupled to a word line; and
each of the second bit cells further comprises:
two inverters cross coupled between a storage node and a complementary storage node, each of the two inverters comprising a single fin finFET pull up transistor coupled between the second cell positive voltage supply CVdd and one of the storage nodes and a multiple fin finFET pull down transistor coupled between the respective one of the storage nodes and a cell negative voltage supply CVss; and
a pair of pass gates coupled between a respective one of a bit line and a complementary bit line and a corresponding one of the storage node and the complementary storage node, each pass gate further comprising a multiple fin finFET transistor with a gate coupled to a word line.

### Claim 8 (depends on 7)

The method of claim 7, wherein the first voltage control circuit is a write assist circuit comprising an input coupled to a periphery Vdd power line, an output coupled to the first cell positive voltage supply CVdd, and an enable input, the enable input having a read state indicating a read cycle and a write state indicating a write cycle.

### Claim 9 (depends on 8)

The method of claim 8, further comprising performing a write cycle, wherein during the write cycle, the first voltage control circuit outputs a CVdd voltage lower than the periphery Vdd power line.

### Claim 10 (depends on 8)

The method of claim 8, further comprising performing a read cycle, wherein during the read cycle, the first voltage control circuit outputs a CVdd voltage equal to or higher than the periphery Vdd power line.

### Claim 11 (depends on 8)

The method of claim 8, further comprising:
performing a write cycle, wherein during the write cycle a word line voltage to the first bit cells is equal to the periphery Vdd power line; and
outputting a CVdd voltage from the first voltage control circuit that is lower than the word line voltage by at least 50 millivolts.

### Claim 12

A method comprising:
applying a first voltage level to a first array of SRAM cells, the SRAM cells of the first array including only single fin finFET transistors formed on a substrate, and to a second array of SRAM cells, the SRAM cells of the second array including single fin finFET transistors and multiple fin finFET transistors formed on the substrate;
applying a word line voltage level to a word line associated with the first array of SRAM cells; and
lowering the first voltage level applied to the first array of SRAM cells to a level lower than the word line voltage level during an operation to write data to the first array of SRAM cells.

### Claim 13 (depends on 12)

The method of claim 12, further comprising lowering the first voltage level applied to both the first array of SRAM cells and the second array of SRAM cells during a standby cycle.

### Claim 14 (depends on 13)

The method of claim 13, wherein the first voltage level is lowered to a level of about 200 mV to about 600 mV.

### Claim 15 (depends on 12)

The method of claim 12, further comprising increasing the first voltage level applied to the first array of SRAM cells to a level higher than the word line voltage level during an operation to read data from the first array of SRAM cells.

### Claim 16 (depends on 12)

The method of claim 12, further comprising maintaining the first voltage level at a level approximately equal to the word line voltage level during an operation to write data to the second array of SRAM cells and an operation to read data from the second array of SRAM cells.

### Claim 17 (depends on 12)

The method of claim 12, wherein the second array of SRAM cells includes pull up transistors formed of single fin finFET transistors and pull down transistors formed of multiple fin finFET transistors.

### Claim 18 (depends on 12)

The method of claim 12, further comprising using the first array of SRAM cells for an application requiring high cell density and using the second array of SRAM cells for an application requiring high data access speed.

### Claim 19 (depends on 12)

The method of claim 12, further comprising applying to a control circuit a high voltage level and a low voltage level and applying to the first array of SRAM cells a selected one of the high voltage level and the low voltage level in response to an enable control signal.

### Claim 20 (depends on 12)

The method of claim 12, further comprising forming the first array of SRAM cells and the second array of SRAM cells on the substrate, and forming a processor circuit on the substrate.